The present invention relates to a computing device for executing a first cryptographic operation of a cryptographic process on useful input data, said computing device comprising a first processor, a second processor and a selection circuit wherein: said selection circuit is configured: for receiving, from an input bus, expanded input data obtained by interleaving dummy input data with said useful input data, for determining positions of the dummy input data in said expanded input data, and for extracting said dummy input data and said useful input data from the expanded input data based on said determined positions, said first processor is configured for executing said first cryptographic operation of said cryptographic process on said extracted useful input data to obtain useful output data, said second processor is configured for executing a second operation on said extracted dummy input data to obtain dummy output data, said computing device being configured for having said operations executed such that leakage generated by said first cryptographic operation is jammed by leakage generated by the second operation.

A chassis is disclosed. The chassis may include a processor, a switch, and at least one storage device in communication with a remote processor. The storage device may support an active power mode and a low power mode. A response to a Keep Alive (KA) message may be sent to the remote processor on behalf of the storage device when the storage device is in low power mode.

Systems, apparatuses, and methods for efficient data transfer in a computing system are disclosed. A source generates packets to send across a communication fabric (or fabric) to a destination. The source generates partition enable signals for the partitions of payload data. The source negates an enable signal for a particular partition when the source determines the packet type indicates the particular partition should have an associated asserted enable signal in the packet, but the source also determines the particular partition includes a particular data pattern. Routing components of the fabric disable clock signals to storage elements assigned to store the particular partition. The destination inserts the particular data pattern for the particular partition in the payload data.

A chassis is disclosed. The chassis may include a processor, a switch, and at least one storage device in communication with a remote processor. The storage device may support an active power mode and a low power mode. A response to a Keep Alive (KA) message may be sent to the remote processor on behalf of the storage device when the storage device is in low power mode.

Technology described herein provides an improved system architecture for offloading infrastructure tasks using a multi-root switch with logic to route, via a switch, application data in a data transfer message between a physical storage device and a host system, the host system interfacing with a virtual function of an IPU, by remapping a transaction identifier field in the data transfer message between a first transaction identifier associated with the virtual function and a second transaction identifier associated with the physical storage device, where the physical storage device is managed by the IPU, and where to route the application data between the host system and the physical storage device includes to bypass temporary storage of the application data in a memory local to the IPU. In some examples a remapping table holds the first transaction identifier and the second transaction identifier.

A multi-chip system and a data transmission method thereof are provided. The multi-chip system includes a first chip, a link unit, and a second chip. The first chip includes multiple transmitter (TX) channels and a first data processing module. The TX channels are configured to provide at least one transaction information. The first data processing module converts the at least one transaction information into at least one first data packet according to a general packet format and packs the at least one first data packet according to a specific packet format to generate a second data packet. The first data processing module merges two sets of second data packets into a third data packet and transmits the third data packet to the link unit. The second chip receives the third data packet through the link unit.

An information handling system includes a first device having a first data communication interface connected to a first socket area of a socket. A second device includes a second data communication interface connected to a second socket area of the socket. A host processor includes a third data communication interface connected to a third socket area of the socket. When an interposer is installed into the socket in a first orientation, the interposer connects the first data communication interface to the third data communication interface. When the interposer is installed into the socket in a second orientation, the interposer connects the first data communication interface to the second data communication interface.

A processing element includes an input zero detector to detect whether the input from the neighbor processing element contains a zero. When the input from the neighbor processing element contains the zero, a zero disable circuit controls the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the arithmetic logic unit for the operation. A controller of an array of processing elements adds a row of error-checking values to a matrix of coefficients, each error-checking value of the row of error-checking values being a negative sum of a respective column of the matrix of coefficients. The controller controls a processing element to perform an operation with the matrix of coefficients and an input vector to accumulate a result vector. Owing to the error-checking values, when a sum of elements of the result vector is non-zero, an error is detected.

A communication system comprising: a digital serial bus, and a master device and at least one slave device connected to the bus. The master and the slave(s) are adapted to communicate according to a predefined communication protocol. The master is adapted for transmitting a continuous bitstream in the form of a plurality of frames, such that each frame comprises one or more words. Each word has a constant time duration, with the first word of each frame being a unique word transmitted by the master for indicating the start of a frame. One or more bits each word is transmitted by the master as a dominant bit; a non-dominant bit, for allowing the at least one slave to overwrite. The at least one slave is adapted for overwriting in the continuous bitstream some non-dominant bits to transmit data in a quasi-synchronous manner.

Systems, apparatuses, and methods for efficient data transfer in a computing system are disclosed. A source generates packets to send across a communication fabric (or fabric) to a destination. The source generates partition enable signals for the partitions of payload data. The source negates an enable signal for a particular partition when the source determines the packet type indicates the particular partition should have an associated asserted enable signal in the packet, but the source also determines the particular partition includes a particular data pattern. Routing components of the fabric disable clock signals to storage elements assigned to store the particular partition. The destination inserts the particular data pattern for the particular partition in the payload data.