Software configuration deployment techniques for disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method includes presenting a user interface configured to receive instructions related to deployment of software to compute units, and receiving user selections of a software element for deployment to a compute unit comprising a processing element and a storage element. Responsive to the user selections, the method includes instructing a management processor of a communication fabric to deploy the software element for use by the compute unit by at least establishing a first partitioning in the communication fabric between the management processor and the storage element, deploying the software element to the storage element using the first partitioning, de-establishing the first partitioning, and establishing a second partitioning in the communication fabric between the processing element and the storage element comprising the software element, wherein the processing element operates using the software element.

A parameter setting apparatus includes a first display device, a first operation controller, a mode operation controller configured to receive either designation of a first adjustment mode for adjusting a send level or a second adjustment mode for adjusting a first parameter other than the send level, and a processing controller. The controller includes a processor. The processor controls the first display device to display a bus selection screen on the display device, selects a bus based on an operation on the displayed selection screen, causes the first operation controller to adjust a send level of the selected bus upon the mode operation controller receiving the designation of the first adjustment mode, and causes the first operation controller to adjust the first parameter upon the mode operation controller receiving the designation of the second adjustment mode.

A method for timestamping and synchronization with high-accuracy timestamps in low-power sensor systems is provided. The method is performed by a device and includes: receiving, by a sensor hub of the device, an interrupt signal from a sensor and performing an interrupt service routine (ISR) to obtain an interrupt timestamp obtained by a latch, wherein the interrupt timestamp is obtained from an always-running unified time reference; obtaining, by the sensor hub, sensor data from the sensor; predicting, by the sensor hub, a prediction timestamp based on an amount of sensor data and the interrupt timestamp by using a filtering algorithm; and correcting, by the sensor hub, a timestamp of each sensor data based on the prediction timestamp.

A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

A method of identifying an unsupported storage device on a server is disclosed as including providing the server with a baseboard management controller (BMC), the BMC obtaining vital product data (VPD) from a storage device on the server, the BMC comparing the VPD from the storage device with one or more approved VPDs, and the BMC issuing an output in response to said comparison.

An electronic control device includes: a first processing unit; a second processing unit; and a transfer control unit. The second processing unit requires a longer time for an activation process than the first processing unit, the transfer control unit includes a communication unit capable of transferring communication data received from an outside to the first processing unit and the second processing unit, the first processing unit includes a first control part that processes the communication data transferred from the transfer control unit, the second processing unit includes a second control part that processes the communication data transferred from the transfer control unit, and the transfer control unit does not set the second processing unit as a transfer destination of the communication data and sets the first processing unit to be included in the transfer destination until the activation process of the second processing unit is completed and sets at least the second processing unit as the transfer destination of the communication data when the activation process of the second processing unit is completed.

An example adapter device includes a host-side connector to connect to a host device, the host-side connector including a host-side electrical contact to connect to a corresponding electrical contact of the host device. The adapter device further includes a storage-side connector to connect to storage devices operable under different protocols, the storage-side connector including a storage-side electrical contact to connect to a connected storage device. The adapter device further includes a circuit to apply a bias voltage to the host-side electrical contact. The host-side electrical contact is to provide a protocol-indicating voltage to indicate to the host device a protocol of the connected storage device. The protocol-indicating voltage is dependent on the connected storage device's influence on the bias voltage.

A PCIe-based communications method includes: a root complex writes identity information of a second node into a first node and writes routing table information into a third node, where the first node is a source node of first data, the second node is a destination node of the first data, and the third node is a node through which the first data arrives at the second node.

Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.

A bus interconnection system and a method for detecting bad routing by the same are provided. The bus interconnection system includes a master node, destination nodes, and a first order switch node. The destination nodes include slave nodes, the bus interconnection system assigns an identification symbol to each of the destination nodes, and adds a destination identification symbol to data sent to the slave nodes by the master node through the first order switch node. When the first order switch node receives the data, the first order switch node updates the destination identification symbol of the data according to a payload of the data, and when one of the destination nodes receives the data, the one of the destination nodes determines whether a bad routing occurs by checking whether the destination identification symbol is equal to the identification symbol assigned to the destination node that receives the data.