Patent classifications
G06F13/4022
FLIGHT RECORDER SYSTEM AND METHOD
A flight recorder system of an aircraft includes a resource controller module (RCM) communicatively coupled, via a switch fabric, to a set of flight recorder system modules (FRM). Each FRM comprises a respective control module, a respective local memory, and a respective set of input and output (I/O) ports communicatively coupled to the switch fabric. The RCM is configured to detect a respective FRM coupled to the switch fabric, and based on the detection, configure an operation of the FRM, and wherein the respective local memory of the FRM is readable by the RCM, and shareable with the other FRMs via the switch fabric.
CROSS BUS MEMORY MAPPING
A computerized system for efficient interaction between a host, the host having a first operating system, and a second operating system, the system comprising a subsystem on the second operating system which extracts data, directly from a buffer which is local to the host, wherein the system is operative for mapping memory from one bus associated with the first operating system to a different bus, associated with the second operating system and from which different bus the memory is accessed, thereby to emulate a connection between the first and second operating systems by cross-bus memory mapping.
Enhancing diagnostic capabilities of computing systems by combining variable patrolling API and comparison mechanism of variables
Methods and apparatus relating to enhancing diagnostic capabilities of computing systems by combining variable patrolling Application Program Interface (API) and comparison mechanism of variables are described. In one embodiment, a first processor core executes a first instance of a workload to generate a first set of safety variables. A second processor core executes a second instance of the workload to generate a second set of safety variables. A third processor core generates a signal in response to comparison of the first set of safety variables and the second set of safety variables. Other embodiments are also disclosed and claimed.
Set diagnostic parameters command
A set command is issued to transfer a diagnostic parameter record to a communication component of the computing environment. The diagnostic parameter record specifies a diagnostic action to be taken by the communication component to obtain diagnostic information and specifies a version of the diagnostic information to be obtained. Based, in part, on issuing the set command, the diagnostic information is obtained. The version of the diagnostic information obtained is the version specified, based on the version specified being supported by the communication component.
Performance monitor for interconnection network in an integrated circuit
Channel availability information associated with data traffic between a Master and a Slave within an interconnection network (“ICN”) in a System-on-Chip (“SoC”) is monitored by a channel performance monitor in order to improve the performance of the ICN. The channel availability information is fed back to certain Masters to control their data traffic into the ICN. The channel performance monitor monitors and evaluates the data traffic handled by switches within the ICN that can potentially interfere with communication paths between particular Masters and Slaves, and control the initiation of data traffic from predetermined Masters.
OPEN-DRAIN BUS REPEATER AND SYSTEM COMPRISING THE SAME
A repeater for open-drain bus communication and a system including the same is provided. The bus repeater includes an A-to-B buffer to receive the signal at the A-side terminal and to produce a first buffered signal, a B-side pull-down control unit to produce a first control signal based on the received first buffered signal, and a B-side pull-down element to pull down the voltage at the B-side terminal based on the first control signal. The B-side pull-down element includes a B-side pull-down transistor that is arranged in between the B-side terminal and a B-side ground reference terminal. The first control signal controls a voltage at the control terminal of the B-side pull-down transistor. The B-side pull-down control unit includes a B-side comparing unit to compare the voltage at the B-side terminal to a first reference voltage, and to generate the first control signal based on a result of the comparison.
SYSTEM PROVIDING A NETWORK INTERFACE TO A PLURALITY OF ELECTRONIC COMPONENTS
A system provides a network interface to electronic components. The system comprises a rack, having a plurality of rack stages, each of which is configured to receive a corresponding electronic component. One peripheral component interconnect express (PCIe) connector corresponds to each rack stage and is connectable to the corresponding electronic component when received in the rack stage. The PCIe connectors are assembled in a PCIe connector group. Each PCIe connector of the PCIe connector group has a same number of active serial links. The system also comprises a network adaptor that provides a serial link termination for each active serial link of the PCIe connector group. The network adaptor comprises a communication interface for communicating with a network. The network adaptor is configured to multiplex signals exchanged between the network and the PCIe connectors of the PCIe connector group.
PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) INTERFACE DEVICE AND METHOD OF OPERATING THE SAME
A peripheral component interconnect express (PCIe) interface device is provided to include: a root complex configured to support a PCIe port, a memory connected to an input/output structure through the root complex, a switch connected to the root complex through a link and configured to transmit a transaction, and an end point connected to the switch through the link to transmit and receive a packet. The PCIe interface device may perform a link power management by changing a state of the link in response to a detection of an idle state of the link.
System and method for energy-efficient implementation of neural networks
A system and method for enhancing C*RAM, improving its performance for known applications such as video processing but also making it well suited to low-power implementation of neural nets. The required computing engine is decomposed into banks of enhanced C*RAM each having a SIMD controller, thus allowing operations at several scales simultaneously. Several configurations of suitable controllers are discussed, along with communication structures and enhanced processing elements.
Multi-core I/O trace analysis
Improved mechanisms and techniques for recording and aggregating trace information from multiple computing modules of a storage system may be provided. On a storage system having multiple computing modules, where each computing module has multiple processing cores, processing cores may record trace information for I/O operations in dedicated local memory—i.e., memory in the same computing module as the processing core that is dedicated to the computing module. One of the processing cores may be configured to aggregate trace information from across multiple computing modules into its dedicated local memory by accessing trace information from the dedicated local memories of the other computing modules in addition to its own. The aggregated information in one dedicated local memory then may be analyzed for functionality and/or performance and additional action taken based on the analysis.