A module for managing communication among instrumentation and control devices associated with a system, and a method for using the module, enable interconnection of various devices across multiple network buses, and filtering of messages travelling between devices on disparate buses. Buses may be established wirelessly in addition to via wired connections. Additional devices may connect to a pluggable terminal interface integrated with the module. The terminal interface may connect to a configurable variety of interconnecting circuits appropriate for various types of terminal devices. An associated user interface may enable a user to configure various parameters pertaining to connected devices, including alerts to be issued when certain parameters exceed thresholds, and actions to be taken upon issuance of such alerts.

Embodiments herein describe a SoC that includes a NoC that supports both strict and relax ordering requests. That is, some applications may require strict ordering where requests transmitted from the same ingress logic to different egress logic blocks are performed sequentially. However, other applications may not require strict ordering, such as interleaved writes to memory. In those applications, relax ordering can be used were the same ingress logic block can transmit multiple requests to different egress logic blocks in parallel. For example, an ingress logic block may receive a first request that is indicated as being a relaxed ordered request. After transmitting the request to an egress logic block, the ingress logic block may receive a second request. The ingress logic block can transmit the second request to a different egress logic block without waiting for a response for the first request.

A communication system includes a camera module and a backend module. The camera module includes an image sensor, a data converter, and a first interface. The image sensor generates a digital signal according to an optical signal. The data converter converts the digital signal into a conversion signal. The first interface transmits the conversion signal. The backend module includes a second interface and a processor. The second interface receives the conversion signal. The processor processes the received conversion signal.

A storage device is disclosed. The storage device may include a storage for a data and a controller to process an input/output (I/O) request from a host processor on the data in the storage. A computational storage unit may implement at least one service for execution on the data in the storage. A command router may route a command received from the host processor to the controller or the computational storage unit based at least in part on the command.

Systems, methods and computer software are disclosed for fronthaul. In one embodiment a method is disclosed, comprising: providing a virtual Radio Access Network (vRAN) having a centralized unit (CU) and a distributed unit (DU); and interconnecting the CU and DU over an Input/Output (I/O) bus using Peripheral Component Interconnect-Express (PCIe); wherein the CU and the DU include a PCI to optical converter and an optical to PCI converter.

Methods, apparatus, systems, and articles of manufacture are disclosed herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem includes a first scheduler, a first hardware accelerator coupled to the first scheduler to process at least a first data element and a second data element, and a first load store engine coupled to the first hardware accelerator, the first load store engine configured to communicate with the first scheduler at a superblock level by sending a done signal to the first scheduler in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.

An integrated circuit for allowing a band of an external memory to be effectively used in processing a layer algorithm is disclosed. One aspect of the present disclosure relates to an integrated circuit including a first arithmetic part including a first arithmetic unit and a first memory, wherein the first arithmetic unit performs an operation and the first memory stores data for use in the first arithmetic unit and a first data transfer control unit that controls transfer of data between the first memory and a second memory of a second arithmetic part including a second arithmetic unit, wherein the second arithmetic part communicates with an external memory via the first arithmetic part.

A system-in-package architecture in accordance with aspects includes a logic die and one or more memory dice coupled together in a three-dimensional slack. The logic die can include one or more global building blocks and a plurality of local building blocks. The number of local building blocks can be scalable. The local building blocks can include a plurality of engines and memory controllers. The memory controllers can be configured to directly couple one or more of the engines to the one or more memory dice. The number and type of local building blocks, and the number and types of engines and memory controllers can be scalable.

A method for operating a transfer device for a differential bus system, including a first bus connection and a second bus connection for connecting to a transfer medium of the differential bus system. The method includes: ascertaining a first variable that characterizes a voltage associated with a first bus line of the bus system, ascertaining a second variable that characterizes a voltage associated with a second bus line of the bus system, ascertaining a third variable that characterizes a sum of the first variable and the second variable for a first bus state, ascertaining a fourth variable that characterizes a sum of the first variable and the second variable for a second bus state, the second bus state being different from the first bus state.

Placement of bridges connecting CAE tools and virtual ECU simulation tools is facilitated. A virtual developmental environment apparatus includes a processing execution unit and a memory for storing a MILS model including a controller block and a plant block, first setting information, a program for realizing a function in the controller block used in executing simulation of the virtual ECU, and second setting information. The processing execution unit identifies a controller block in the MILS model based on the first setting information, arranges a bridge for connecting the input port and the output port and the I/O port of the virtual ECU to the input port and the output port of the identified controller block, and connects the bridge and the I/O port of the virtual ECU based on the second setting information.