A method of operating a Peripheral Component Interconnect Express (PCIe) device including a first port and a second port comprises: performing a first link training operation to link up a first host with a first link of the first port; operating in a single port mode when the first link training operation is completed; performing a lane reduce operation to reduce a lane corresponding to the first link in response to a mode change request received from the first host; and performing a second link training operation to link up a second host with a second link of the second port when a status of the first link is an L0 state.

An electronic device comprises a bridge configured to transfer data bus transactions from a transaction source domain having a first bus width to a transaction target domain having a second bus width less than the first bus width. The bridge comprises a first interface configured to receive a transaction from the transaction source domain, where the transaction has a first transaction burst length. A converter logic is configured such that when a transaction is received via the first interface, the converter logic splits the transaction into a plurality of second transactions each having a respective second transaction burst length, wherein the plurality of second transactions have the second bus width. A second interface is configured to send the plurality of second transactions to the transaction target domain.

A trace network for debugging integrated circuits is disclosed. At least one functional network includes a plurality of components interconnected by a number of network switches, implemented on at least one integrated circuit. A trace network is also implemented on the at least one integrated circuit, and includes a plurality of trace circuits configured to generate trace data based on transactions between ones of the plurality of components. The plurality of trace circuits are coupled to one another by a plurality of trace network switches. The trace circuits are configured to convey the generated trace data to an interface, via the trace network, without using the at least one functional network.

Systems, methods, and apparatuses relating to operations in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value, a plurality of input queues, an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value, a plurality of output queues, and an output controller to control enqueue and dequeue of values into the plurality of output queues according to the configuration value.

Methods and apparatus for efficient scaling of fabric architectures such as those based on PCIe technology, including up to very large fabrics and numbers of hosts/devices for use in ultra-high performance applications such as for example data centers and computing clusters. In one aspect, methods and apparatus for using Non-Transparent Bridge (NTB) technology to export Message Signaled Interrupts (MSIs) to external hosts are described. In a further aspect, an IO Virtual Address (IOVA) space is created is used as a method of sharing an address space between hosts, including across the foregoing NTB(s). Additionally, a Fabric Manager (FM) entity is disclosed and utilized for programming e.g., PCIe switch hardware to effect a desired host/fabric configuration.

A portable information handling system interacts with haptic devices of a game controller though a direct wired interface when the game controller couples to opposing sides of the information handling system and through a wireless interface when the game controller couples to a bridge having a wired interface to communicate with the game controller and a wireless interface to communicate with the information handling system. The haptic devices provide a first haptic response associated with a desired vibration for a weight of game controller and information handling system when the game controller couples directly to the information handling system, and a second haptic response associated with the desired vibration for a weight of the game controller and bridge when the game controller couples directly to the bridge for wireless communication with the information handling system.

A port configuration migration system includes a primary I/O module connected to a server device via a secondary I/O module. A fabric manager system maps a virtual interface to a first downlink port on the primary I/O module that is connected to the secondary I/O module, with the virtual interface providing a virtual direct connection to the server device. The fabric manager system then configures the virtual interface with communication configuration information for the server device such that communications received via the first downlink port are transmitted using the virtual interface. The fabric manager system then receives a discovery communication from the server device via a second downlink port on the primary I/O module that is connected to the secondary I/O module, and remaps the virtual interface to the second downlink port such that communications received via the second downlink port are transmitted using the virtual interface.

A method for communicating between a master and a plurality of slaves includes generating a communication frame including generating a slave data frame in each slave. The slave data frame has a data packet including one or more data bytes and at least one gap of variable time length comprising no information in the slave data frame. The gap may be at the beginning of said slave data frame before the beginning of the first data byte of said data packet and/or at the end of said data packet after the end of a last data byte of said data packet, where the gaps have a time length dependency based on parameters locally stored in each of said at least one slave. The slave data frame is transmitted sequentially where the gap increases for each subsequent slave.

A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via an active bridge chiplet. The active bridge chiplet is an active silicon die that bridges GPU chiplets and allows partitioning of systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

A computing system that enables data stored in a persistent memory region to be preserved when a processor fails can include volatile memory comprising the persistent memory region, non-volatile memory, and a system on a chip (SoC). The SoC can include a main processor that is communicatively coupled to both the volatile memory and the non-volatile memory. The SoC can also include an auxiliary processor that is communicatively coupled to both the volatile memory and the non-volatile memory. The SoC can also include instructions that are executable by the auxiliary processor to cause the data in the persistent memory region of the volatile memory to be transferred to the non-volatile memory in response to a failure of the main processor.