G06F15/17306

SERVER BASEBOARD, SERVER, CONTROL METHOD, ELECTRONIC APPARATUS AND READABLE MEDIUM
20220147364 · 2022-05-12 ·

The present disclosure provides a server baseboard, relates to the field of computer technology and can be applied to the fields of cloud computing and big data. A specific implementation scheme is that the server baseboard includes: a main control program module, a switch chip connected to the main control program module, and a plurality of physical network ports for connecting the switch chip to a management network and a baseboard other than the baseboard where the main control program module is located. The server baseboard can reduce the construction cost of the management network, and improve the availability of a server and the security of a service network. The present disclosure also provides a server, a control method, an electronic apparatus, and a readable medium.

DATA ACTOR AND DATA PROCESSING METHOD THEREOF
20220129408 · 2022-04-28 ·

Provided is a data actor, which is in data communication with direct upstream actor and/or downstream actor. The data actor includes a message bin, a finite state machine, a processing component and an output data cache. The message bin is configured to receive a message from the upstream actor and/or the downstream actor; the finite state machine is configured to change a current state of the actor based on the received message in the message bin and an operation of the processing component; when a state of the finite state machine reaches a trigger condition, the processing component directly reads output data in a readable state in an output data cache of the upstream actor and executes a predetermined operation, and then stores result data subsequent to execution of the predetermined operation in an output data cache of the data actor.

COMPUTING DEVICE AND COMPUTING SYSTEM
20230244630 · 2023-08-03 ·

A computing device and a computing system are provided. The computing device comprises: a plurality of computing modules; and serial communication paths between/among the plurality of computing modules. Each computing module comprises: an internal circuit for performing an operation on a signal received from a corresponding serial communication path; and an extension circuit for receiving a signal from the internal circuit as an input signal. The extension circuit comprises: a delay module for delaying the input signal, the delay module comprising one or more delay units; one or more extension select modules for selectively performing a level extension on the input signal through the signal delayed by corresponding one or more delay units to generate one or more respective level-extended signals; and an output module for outputting one or more of the one or more level-extended signals.

Receiver-directed computer network congestion control system

A receiver-directed congestion control system which provides receiver-directed apportioning by adding a bandwidth share indicator value to the acknowledgement messages sent by the receiver to the senders. In certain embodiments, bandwidth share indicator value comprises the number of senders seen by the receiver. In other embodiments, the bandwidth share indicator value may comprise a percentage bandwidth share allocated to the sender computer to allow for varying priorities between senders. In the acknowledgement message, each sender may also include the incast degree, which is programmed in the application, to the receiver. This strategy enables the receiver to send back the sender count to all the senders as soon the first sender's packets arrive, even before the rest of the senders' packets arrive. Thus, the sender count and the incast degree look-ahead enable the receiver-directed system to achieve accurate and faster convergence of sending rates, without any repeated adjustments.

METHOD FOR MANAGING THE OPERATION OF A SYSTEM ON CHIP, AND CORRESPONDING SYSTEM ON CHIP
20230291645 · 2023-09-14 ·

System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.

Systems and methods for automatically updating compute resources

Systems and methods for automatically removing and replacing outdated compute resources in a cluster. The systems and methods include a configurable monitoring system that is configured to detect outdated compute resources and trigger a cycling process to automatically replace the detected outdated compute resources with new compute resources. The disclosed systems and methods safely rotate a group of compute resources by identifying and detaching outdated compute resources, waiting until the outdated compute resources have been drained of pending jobs scheduled on these resources, waiting until replacement compute resources have started and then cordoning, draining, deleting and terminating the outdated compute resources.

ELECTRONIC COMPUTING DEVICE

The computing efficiency of an electronic computing device is improved. HPCs 20 to 23 include arithmetic processing units HA0 to HA3, respectively. Each of the arithmetic processing units HA0 to HA3 executes arithmetic processing in parallel. LPCs 30 to 33 includes management processing units LB0 to LB3, respectively. Each of the management processing units LB0 to LB3 manages execution of specific processing by an accelerator 6 when each of the arithmetic processing units HA0 to HA3 causes the accelerator 6 to execute the specific processing, and performs a series of commands for causing the accelerator 6 to execute the specific processing on a DMA controller 5 and the accelerator 6.

Techniques for ascribing social attributes to content

Techniques for ascribing social attributes to content items and for selecting content to display in a content feed are described. According to various embodiments, accessing one or more content items accessible via a network are accessed, each of the content items having received one or more social activity signals. Thereafter, members of an online social network service that submitted the social activity signals may be identified. Member profile data identifying member profile attributes of the members cemented the social activity signals may then be accessed. Thereafter, social attribute information may be generated and associated with each of the content items, the social attribute information identifying the member profile attributes of the members that submitted the social activity signals associated with each of the content items.

FACILITATING RESOURCE FREQUENCY MANAGEMENT FOR EMERGENCY RESPONSE
20220117033 · 2022-04-14 ·

Resource frequency management is facilitated. For instance, information is received indicative of an emergency condition in a defined area and a command is transmitted to a network device for the defined area to cause the base station device to send a communication for the emergency condition via a first wireless communication channel with a mobile device of mobile devices associated with a subscriber identity of respective subscriber identities assigned to provide a response to the emergency condition.

Signal pathways in multi-tile processors

Embodiments herein may present a multi-tile processor including a plurality of processor tiles, and a plurality of interconnects selectively coupling the plurality of processor tiles to each other. A first processor tile may include a memory to store a bulletin board to hold a message, an execution unit, and an encapsulated software module. The encapsulated software module may select a second processor tile coupled with the first processor tile by an interconnect to be a part of a signal pathway. The second processor tile may be selected based on a selection criterion of the signal pathway and the message held in the bulletin board. The encapsulated software module may post and read a message at the bulletin board stored in the memory, or read a message from a bulletin board stored in a memory of the second processor tile. Other embodiments may be described and/or claimed.