Systems, apparatuses, and methods for performing real-time video rendering with performance guaranteed power management are disclosed. A system includes at least a software driver, a power management unit, and a plurality of processing elements for performing rendering tasks. The system receives inputs which correspond to rendering tasks which need to be performed. The software driver monitors the inputs that are received and the number of rendering tasks to which they correspond. The software driver also monitors the amount of time remaining until the next video synchronization signal. The software driver determines which performance setting will minimize power consumption while still allowing enough time to finish the rendering tasks for the current frame before the next video synchronization signal. Then, the software driver causes the power management unit to provide this performance setting to the plurality of processing elements as they perform the rendering tasks for the current frame.

A control circuit for a switching converter is described herein. In accordance with one embodiment the control circuit includes an analog bus that receives a plurality of input signals and a first set of functional units that are operable to receive at least some of the input signals via the analog bus and to process the input signals to generate digital output data based on the input signals. The control circuit further includes an event bus that has an event bus controller and a plurality of bus lines and a second set of functional units that are operable to receive the output data, via the event bus, from the functional units of the first set. At least one functional unit of the second set of functional units is operable to determine switching time instants for the switching converter based on the output data received via the event bus, and the event bus controller includes an arbiter operable to arbitrate data transmission across the bus lines.

A system on chip (SoC) includes a processor configured to execute code corresponding to at least one application and a performance controller configured to generate control information for controlling performance of the processor for each function to be executed by the processor by using a history table in which a plurality of history performance information items respectively corresponding to a plurality of functions included in the code are stored and to generate a control signal corresponding to the control information.

A data processing node includes a management environment, an application environment, and a shared memory segment (SMS). The management environment includes at least one management services daemon (MSD) running on one or more dedicated management processors thereof. One or more application protocols are executed by the at least one MSD on at least one of the dedicated management processors. The management environment has a management interface daemon (MID) running on one or more application central processing unit (CPU) processors thereof. The SMS is accessible by the at least one MSD and the MID for enabling communication of information of the one or more application protocols to be provided between the at least one MSD and the MID. The MID provides at least one of management service to processes running within the application environment and local resource access to one or more processes running on another data processing node.

A method includes reading first and second timer count values from a timer, wherein the first timer count value is associated with a first time point and the second timer count value is associated with a second time point, calculating a difference between the first and the second timer count values, and determining whether the difference is within a range, wherein the range is based on a desired executing frequency to perform a computing task, a variation of the desired executing frequency, and a timer frequency. Further, based on the difference not being within the range, the method includes setting an error flag value to be true and incrementing an error count value.

Apparatus and methods for coordinating a configuration of a microcontroller system is provided. An exemplary method includes determining a set of configuration data of a plurality of sets of configuration data. The plurality of sets of configuration data are associated with at least one operational unit, wherein the at least one operational unit is associated with the microcontroller system. Each set of the plurality of sets of configuration data defines a configuration of the at least one operational unit, and each set comprises coordination information to coordinate a transition to the configuration of the at least one operational unit. The method further includes configuring the microcontroller system corresponding to the determined set of configuration data. Configuring the microcontroller system includes coordinating the transition to the configuration according to the coordination information. The coordinating employs one or a plurality of coordination states, wherein each coordination state is associated with at least partly configuring the at least one operational unit according to the configuration, and/or configuring the at least one operational unit by an intermediate configuration.

A data processing node includes a management environment, an application environment, and a shared memory segment (SMS). The management environment includes at least one management services daemon (MSD) running on one or more dedicated management processors thereof. One or more application protocols are executed by the at least one MSD on at least one of the dedicated management processors. The management environment has a management interface daemon (MID) running on one or more application central processing unit (CPU) processors thereof. The SMS is accessible by the at least one MSD and the MID for enabling communication of information of the one or more application protocols to be provided between the at least one MSD and the MID. The MID provides at least one of management service to processes running within the application environment and local resource access to one or more processes running on another data processing node.

Aspects of the disclosure are directed to a quality of service (QOS) assignment policy for processor applications in a system on a chip (SoC). In accordance with one aspect, the system on a chip (SoC) includes an applications central processing unit (CPU), wherein the applications CPU comprises a quality of service (QOS) database table configured to list a plurality of QoS metrics associated with a plurality of processor threads, wherein at least one of the plurality of QoS metrics is used to determine a dynamic clock and voltage scaling (DCVS) operating point; a graphics processing unit (GPU) coupled to the applications CPU; and a common interconnection databus coupled to the applications CPU and the GPU.

A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.

The disclosed system obtains records from a database, determines weights associated with the records, and obtains a first and a second force acting on a record among the records. The system defines a projection space based on the records, represents the record in the projection space by projecting the record into the projection space to obtain a projected record, and represents the first force and the second force in the projection space. The system repeatedly applies the first force and the second force to the projected record, thereby changing a position of the projected record in the projection space, until an equilibrium between the first force and the second force is reached. The system determines how closely the value associated with the record satisfies the first value associated with the criterion based on a distance between the projected record in the projection space at equilibrium and the first force.