This disclosure provides a multimedia application processor architecture, comprising a master control system, at least two groups of independent multimedia application processors, at least two groups of common CPU, a power manager, and a common interface and CPU bus, wherein the master control system is connected to each group of the independent multimedia application processors, each group of the common CPU, the power manager, and the common interface and CPU bus respectively, and is configured to control and manage, and provide power control and management for, the at least two groups of independent multimedia application processors, the at least two groups of common CPU, the power manager, and the common interface and CPU bus, each group of the common CPU is connected to the independent multimedia application processors for providing a backup central processor data processing capability for the independent multimedia application processors.

A system-on-chip includes a reconfigurable data interface to prepare data streams for execution patterns of a processing unit in a flexible compute accelerate system. An apparatus is provided that includes a first set of line buffers configured to store a plurality of data blocks from a memory of a system-on-chip and a field composition circuit configured to generate a plurality of data segments from each of the data blocks. The field composition circuit is reconfigurable to generate the data segments according to a plurality of reconfiguration schemes. The apparatus includes a second set of line buffers configured to communicate with the field composition circuit to store the plurality of data segments for each data block, and a switching circuit configured to generate from the plurality of data segments a plurality of data streams according to an execution pattern of a processing unit of the system-on-chip.

The present invention provides an AIoT development system. The present invention includes: an auxiliary device having an AI edge computing processing function, a core, and a plurality of function expansion kits. The core includes: a processing unit having programmable, computing and AI communication functions; and a plurality of expansion interfaces for performing signal transmission with an external device. Each of the function expansion kits includes: a relay interface connected to the expansion interfaces of the core, a transducer for sensing signals from a test object located at where a corresponding one of the function expansion kits is, and a function circuit for processing the signals sensed by the transducer. The transducer of each of the function expansion kits senses signals, or modulates the sensed signals via the function circuit, and sends the sensed signals or the modulated signals to the processing unit through the relay interface and the expansion interfaces.

A method of processing partitions of a tensor in a target order includes receiving, by a reorder unit and from two or more producer units, a plurality of partitions of a tensor in a first order that is different from the target order, storing the plurality of partitions in the reorder unit, and providing, from the reorder unit, the plurality of partitions in the target order to one or more consumer units. In an example, the one or more consumer units process the plurality of partitions in the target order.

This disclosure provides a ZJD multimedia application processor architecture, comprising a ZJD master control system, at least two groups of independent multimedia application processors, at least two groups of common CPU, a power manager, and a common interface and CPU bus, wherein the ZJD master control system is connected to each group of the independent multimedia application processors, each group of the common CPU, the power manager, and the common interface and CPU bus respectively, and is configured to control and manage, and provide power control and management for, the at least two groups of independent multimedia application processors, the at least two groups of common CPU, the power manager, and the common interface and CPU bus, each group of the common CPU is connected to the independent multimedia application processors for providing a backup central processor data processing capability for the independent multimedia application processors.

A system-on-chip comprises: a first sub-circuit having a defined interface and a defined fixed-hardware functionality; a second reconfigurable sub-circuit being signal-connected via the interface to the first sub-circuit; and one or more terminals. The second sub-circuit is configured as an interface circuit between the terminals and the first sub-circuit. The first sub-circuit and the second sub-circuit are split into a plurality of individual first and second circuit blocks. At least one of said first circuit blocks is signal-connected via signal connections, each running through one or more of the second circuit blocks, to one or more other first circuit blocks or one or more of the terminals. One or more of said signal connections are reconfigurable, by the respective one or more second circuit blocks pertaining to the respective signal connection. The SOC is reconfigurable before or during its operation by reconfiguring at least one of said second circuit blocks.

An optical computing device and a computing method are provided, to provide an optical Ising machine with high operation efficiency. The optical computing device includes a first spin array, an optical feedback network, and a second spin array, where the optical feedback network is separately connected to the first spin array and the second spin array. The first spin array may receive a first group of signals including N optical pulses or N electrical signals, and generate a first group of spin signals including N spin signals. The optical feedback network may receive the first group of spin signals, and generate, based on the first group of spin signals and specified first data, a first group of feedback signals including N feedback signals. The first spin array and the second spin array may process a plurality of signals in parallel, to improve computation efficiency of the optical computing device.

An integrated circuit includes a plurality of configurable units, each configurable unit having two or more corresponding sections. The plurality of configurable units is arranged in a serial arrangement to form a chain of sections of the configurable units. A data bus is connected to the plurality of configurable units which communicates data at a clock rate. The chain of sections is to receive and write a series of tensors at the clock rate at a first end section of the chain of sections, and sequentially propagate the series of tensors through individual sections within the chain of sections at the clock rate. The chain of sections is to output the series of tensors at a second end section of the chain of sections. The chain of sections is to also output the series of tensors at an intermediate section of the chain of sections.

The present invention includes an integrated system-on-chip device configured on a substrate member. The device has a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The input/output block comprises a SerDes block, a CDR block, a compensation block, and an equalizer block. The SerDes block is configured to convert a first data stream of N having a first predefined data rate at a first clock rate into a second data stream of M having a second predefined data rate at a second clock rate. The device has a driver module provided on the substrate member and coupled to a signal processing block, and a driver interface provided on the substrate member and coupled to the driver module and a silicon photonics device.

A hybrid electrical and optic system-on-chip (SOC) device configured for both electrical and optic communication includes a substrate, an electrical device configured for electrical communication arranged on the substrate, a photonics device configured for optic communication arranged on the substrate, and a self-test module arranged on the substrate. The self-test module is configured to receive a loop-back signal indicative of an optical signal output from the photonics device and calibrate the photonics device based on the loop-back signal.