A computing system capable of reducing data movement during an embedding operation and efficiently processing the embedding operation includes a host and a memory system. The host divides a plurality of feature tables, each including a respective plurality of embedding vectors for a respective plurality of elements, into a first feature table group and a second feature table group; generates a first embedding table configured of the first feature table group; and sends a request for a generation operation of a second embedding table configured of the second feature table group to the memory system. The memory system generates the second embedding table according to the generation operation request provided by the host. The host divides the plurality of feature tables into the first feature table group and the second feature table group based on the number of elements included in each of the plurality of feature tables.

Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

A processor for supporting PIM (Processing-in-Memory) execution in a multiprocessing environment includes logic configured to: receive a request to initiate an offload of a number of PIM instructions to a PIM device. The request is issued by a first thread of a processor. The logic is also configured to reserve, based on information in the request, resources of the PIM device for execution of the plurality of instructions.

A method and apparatus with process scheduling is provided. The method includes receiving operation requests from a plurality of processes; determining priority information of a plurality of near memory processors based on predetermined state information of a plurality of memories which correspond to the plurality of near memory processors; allocating the received operation requests to at least one near memory processor based on the determined priority information; and updating state information of at least one memory of the plurality of memories corresponding to the at least one near memory processor in a state table.

A memory device supporting a processing-in-memory (PIM) protocol includes a mode register set (MRS) configured to store a first parameter code and a second parameter code regarding the PIM protocol in a first register and a second register, respectively. The first parameter code includes a PIM protocol change code indicating whether a PIM protocol change related to an old version PIM protocol is supported, and the second parameter code includes a PIM protocol code for setting a current operation PIM protocol from among a plurality of PIM protocols. The memory device further includes a PIM circuit configured to perform an internal processing operation based on the current operation PIM protocol.

A processing-in-memory (PIM) device includes memory banks configured to perform a read operation and a write operation in a normal mode, and to perform a first data providing operation in an accelerator mode, a global buffer configured to perform a second data providing operation in the accelerator mode, processing elements configured to perform at least one of a first arithmetic operation and a second arithmetic operation using at least one of the first data and the second data in the accelerator mode, a command decoder configured to output a normal mode control signal or an accelerator mode start signal, and a processor unit configured to store an operation instruction set transmitted from an external device, to transmit the operation instruction set to the processing elements, and to transmit the accelerator mode control signal to the processing elements.

A memory includes two or more portions of memory circuitry and two or more processor in memory (PIM) functional blocks, each PIM functional block associated with a respective portion of the memory circuitry. In operation, at least one other PIM functional block other than a particular PIM functional block copies data from a source location accessible to the other PIM functional block. The other PIM functional block then provides the data to the particular PIM functional block. The particular acquires and stores the data in a destination location accessible to the particular PIM functional block. The particular PIM functional block next performs one or more PIM operations using the data.

Systems, apparatuses, and methods for identifying response data arriving out-of-order from two different memory types are disclosed. A computing system includes one or more clients for processing applications. A memory channel transfers memory traffic between a memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a given point in time when read data is to be scheduled to arrive on the memory bus from memory. The memory controller associates a unique identifier with the given point in time. The memory controller identifies a given command associated with the arriving read data based on the given point in time.

A processing-in-memory (PIM) device includes a plurality of memory banks and a plurality of multiplication/accumulation (MAC) operators. The MAC operators perform MAC arithmetic operations using data output from the plurality of memory banks and input into the MAC operators. A page is allocated to have a first page size in the plurality of memory banks in a memory mode. The page is allocated to have a second page size, which is greater than the first page size, in the plurality of memory banks in a MAC arithmetic mode.

A memory controller includes a memory request queue that stores a memory request associated with a memory device including the first memory die and the second memory die having a shared channel, an address converter that selects one of first and second address mapping tables for the first memory die and the second memory die based on a bit of a physical address of the memory request and converts the physical address into a memory address based on the selected address mapping table and a physical layer that transmits the memory address to the memory device through the channel.