A chip and an interface conversion device are provided. The chip includes first, second, third, fourth, fifth and sixth pads. The first and second pads are coupled to first and second SBU pins of a USB connector respectively. The fourth and the sixth pads are coupled to first and second pins of an AUX channel of a DP connector respectively. When the chip operates in a first mode, first and second AUX channel signals generated by the chip are transmitted to the third and fifth pads respectively, a voltage of the fourth pad is weakly pulled down, and a voltage of the sixth pad is weakly pulled up. When the chip operates in a second mode, one of the first and second pads is connected to the fourth pad, and the other one of the first and second pads is connected to the sixth pad.

A system to support a machine learning (ML) operation comprises a core configured to receive and interpret commands into a set of instructions for the ML operation and a memory unit configured to maintain data for the ML operation. The system further comprises an inference engine having a plurality of processing tiles, each comprising an on-chip memory (OCM) configured to maintain data for local access by components in the processing tile and one or more processing units configured to perform tasks of the ML operation on the data in the OCM. The system also comprises an instruction streaming engine configured to distribute the instructions to the processing tiles to control their operations and to synchronize data communication between the core and the inference engine so that data transmitted between them correctly reaches the corresponding processing tiles while ensuring coherence of data shared and distributed among the core and the OCMs.

A system to support a machine learning (ML) operation comprises a core configured to receive and interpret commands into a set of instructions for the ML operation and a memory unit configured to maintain data for the ML operation. The system further comprises an inference engine having a plurality of processing tiles, each comprising an on-chip memory (OCM) configured to maintain data for local access by components in the processing tile and one or more processing units configured to perform tasks of the ML operation on the data in the OCM. The system also comprises an instruction streaming engine configured to distribute the instructions to the processing tiles to control their operations and to synchronize data communication between the core and the inference engine so that data transmitted between them correctly reaches the corresponding processing tiles while ensuring coherence of data shared and distributed among the core and the OCMs.

A semiconductor structure includes a first processor on a first die of a substrate. There is a second processor on a second die of the substrate. There is a one-time programmable (OTP) memory programming circuit, outside of the first and second die, and shared by the first and second processors. Each of the first and second processors include a one-time programmable (OTP) memory. The OTP memory programming circuit is configured to program each OTP memory.

A microcontroller includes distinct electronic functions and an interconnection circuit capable of transmitting in wireless fashion data between the functions. The microcontroller can be operated by writing configuration characteristics into a memory of the interconnection circuit for electronic functional circuits that do not have configuration characteristics contained in the memory and erasing configuration characteristics from the memory for electronic functional circuits that have configuration characteristics contained in the memory but are determined to not be able to wirelessly communicate with the interconnection circuit. Data can be wirelessly transmitted between the interconnection circuit and electronic functional circuits having configuration characteristics contained in the memory.

Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.

A method, system, and apparatus for setting an on-chip password is provided. In an embodiment, a method for programming an on-chip password includes determining a desired logic state for a field-effect transistor according to the on-chip password. The desired logic state is one of a first logic state and a second logic state. The method also includes subjecting one of a source and a drain of the field-effect transistor to hot-carrier stress according to the desired logic state to produce one of a symmetric state of the field-effect transistor and an asymmetric state of the field-effect transistor. The symmetric state corresponds to one of the first and second logic states. The asymmetric state corresponds to the other one of the first and second logic states.

A semiconductor chip comprises at least one data bus to transmit data processed by the semiconductor chip, an electric potential generator block packaged together with the at least one data bus to be blocked from external light by a package, the electric potential generator block to detect an event in which the package is unable to block the external light, and a switch configured to block a transmission of at least some data in the at least one data bus if the event is detected. A semiconductor chip comprises an energy harvesting element inside a package. The energy harvesting element may comprise an on-chip photodiode. A depackaging attack causes the generation of a voltage of a photodiode, and thus a change in physical state of the packaging can be detected.

The present invention discloses a processor comprising three-dimensional memory (3D-M) array (3D-processor). Instead of logic-based computation (LBC), the 3D-processor uses memory-based computation (MBC). It comprises an array of computing elements, with each computing element comprising an arithmetic logic circuit (ALC) and a 3D-M-based look-up table (3DM-LUT). The ALC performs arithmetic operations on the LUT data, while the 3DM-LUT is stored in at least one 3D-M array.

A semiconductor structure includes a first processor on a first die of a substrate. There is a second processor on a second die of the substrate. There is a one-time programmable (OTP) memory programming circuit, outside of the first and second die, and shared by the first and second processors. Each of the first and second processors include a one-time programmable (OTP) memory. The OTP memory programming circuit is configured to program each OTP memory.