An integrated circuit can include programmable circuitry configured to implement an overlay circuit specified by an overlay. The overlay circuit can include a trace buffer configured to receive a probed signal from circuitry within the overlay circuit. The trace buffer can be configured to generate trace data from the probed signal and store the trace data in a runtime allocated memory. The integrated circuit also can include a processor coupled to the programmable circuitry and configured to control operation of the trace buffer. The processor can be configured to read the trace data from the runtime allocated memory.

A secure semiconductor chip is presented. The semiconductor chip is, for example, a system-on-chip. Processor cores included in the system-on-chip are connected to normal IPs through a system bus. A secure bus, which is a hidden bus physically separated from the system bus, is provided separately. The secure bus is connected to security IPs which perform security functions or handle security data. The secure semiconductor chip may perform necessary authentication by switching a normal mode to a secure mode.

Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.

A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Apparatus and methods for coordinating a configuration of a microcontroller system is provided. An exemplary method includes determining a set of configuration data of a plurality of sets of configuration data. The plurality of sets of configuration data are associated with at least one operational unit, wherein the at least one operational unit is associated with the microcontroller system. Each set of the plurality of sets of configuration data defines a configuration of the at least one operational unit, and each set comprises coordination information to coordinate a transition to the configuration of the at least one operational unit. The method further includes configuring the microcontroller system corresponding to the determined set of configuration data. Configuring the microcontroller system includes coordinating the transition to the configuration according to the coordination information. The coordinating employs one or a plurality of coordination states, wherein each coordination state is associated with at least partly configuring the at least one operational unit according to the configuration, and/or configuring the at least one operational unit by an intermediate configuration.

The present invention provides an arbitrary waveform generator based on instruction architecture. To deal with the feature that the instructions and waveform data of the AWG are coupled in the prior art, an instruction set based waveform synthesis controller is employed, and substitutes for the sequence wave generator in the present invention, i.e. an arbitrary waveform generator based on instruction architecture. Thus the time-sharing scheduling in reading the waveform synthesis instruction and the segment waveform data is realized, and the complexity of the hardware is reduced, so that the AWG in present invention can synthesize and generate a complex sequence wave rapidly and efficiently.

Disclosed are various examples of providing provide efficient waiting for detection of memory value updates for Advanced RISC Machines (ARM) architectures. An ARM processor component instructs a memory agent to perform a processing action, and executes a waiting function. The waiting function ensures that the processing action is completed by the memory agent. The waiting function performs an exclusive load at a memory location, and a wait for event (WFE) instruction that causes the ARM processor component to wait in a low-power mode for an event register to be set. Once the event register is set, the waiting function completes and a second processing action is executed by the ARM processor component.

A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Disclosed is a secure semiconductor chip. The semiconductor chip is, for example, a system-on-chip. The system-on-chip is operated by connecting normal IPs to a processor core included therein via a system bus. A secure bus, which is a hidden bus physically separated from the system bus, is separately provided. Security IPs for performing a security function or handling security data are connected to the secure bus. The secure semiconductor chip can perform required authentication while shifting between a normal mode and a secure mode.