Patent classifications
G06F15/7871
Flexible allocation of I/O channels of a hardware component
A method for generating software for a hardware component of a measuring, control, or regulating system having a processor, an FPGA, and a plurality of I/O channels. The I/O channels are connected to the FPGA and the FPGA is connected to the processor via a communications interface. The method includes the steps of selecting a first subset of the I/O channels for operation by the FPGA, generating a first application for execution in the FPGA, selecting a second subset of the I/O channels for operation by the processor, and generating a second application for execution on the processor. The step of generating a first application comprises generating code for connecting the second subset of I/O channels to the communications interface. The invention relates in addition to a method for operating a hardware component.
RECONFIGURABLE DATA INTERFACE UNIT FOR COMPUTE SYSTEMS
A system-on-chip includes a reconfigurable data interface to prepare data streams for execution patterns of a processing unit in a flexible compute accelerate system. An apparatus is provided that includes a first set of line buffers configured to store a plurality of data blocks from a memory of a system-on-chip and a field composition circuit configured to generate a plurality of data segments from each of the data blocks. The field composition circuit is reconfigurable to generate the data segments according to a plurality of reconfiguration schemes. The apparatus includes a second set of line buffers configured to communicate with the field composition circuit to store the plurality of data segments for each data block, and a switching circuit configured to generate from the plurality of data segments a plurality of data streams according to an execution pattern of a processing unit of the system-on-chip.
Image processing system and image processing apparatus for configuring logical circuit on circuit according to configuration data
An image processing system includes, a reconfigurable circuit, a storage unit storing first configuration data for a first logical circuit in a predetermined area on the reconfigurable circuit, and second configuration data for a second logical circuit in the predetermined area, and a configuration unit configured to perform first configuration processing for configuring the first logical circuit in the predetermined area, by using the stored first configuration data and predetermined configuration data, on the predetermined area and a different area, and to perform second configuration processing for configuring the second logical circuit in the predetermined area, by using the stored second configuration data and predetermined configuration data, on the predetermined area and the different area. The predetermined configuration data used for the first configuration processing and the predetermined configuration data used for the second configuration processing are not stored in a duplicated way.
REMOTE PROGRAMMING SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
Systems and methods for management of remotely programmable, programmable logic devices (remote PLDs) are disclosed. An example system includes a remote PLD including a plurality of programmable logic blocks (PLBs) arranged in a PLD fabric and a programmable input/output (I/O) coupled to the PLD fabric. The remote PLD is configured to form a communications link between the remote PLD and a remote PLD management system node over a communications network via a communication module of the remote PLD or a host device configured to interface with the remote PLD over the programmable I/O. The remote PLD is configured to receive a protected configuration image from the remote PLD management system node over the communications link and programs the PLD fabric according to the protected configuration image.
MANAGING DOCKING STATIONS
A setting to be applied at a docking station is obtained, either from a memory of the docking station, or from another device connected to a network by first obtaining, from a user device connected to the docking station, an identity of the user device and/or an identity of a user of the user device. Based on the identity of the user and/or the user device, a configuration set, of a plurality of configuration sets, that identifies at least one setting to be applied at the docking station is obtained and a setting to apply at the docking station is determined based at least partly on the configuration set. The docking station may store a set of docking station specific settings which can be used in conjunction with the setting(s) determined from the configuration set.
NETWORKED PROGRAMMABLE LOGIC SERVICE PROVIDER
Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a networked server environment. In one example, a system hosting a network service providing field programmable gate array (FPGA) services includes a network service provider configured to receive a request to implement application logic in a plurality of FPGAs, allocate a computing instance comprising the FPGAs in responses to receiving the request, produce configuration information for programming the FPGAs, and send the configuration information to an allocated computing instance. The system further includes a computing host that is allocated by the network service provider as a computing instance which includes memory, processors configured to execute computer-executable instructions stored in the memory, and the programmed FPGAs.
Tensor partitioning and partition access order
A method of processing partitions of a tensor in a target order includes receiving, by a reorder unit and from two or more producer units, a plurality of partitions of a tensor in a first order that is different from the target order, storing the plurality of partitions in the reorder unit, and providing, from the reorder unit, the plurality of partitions in the target order to one or more consumer units. In an example, the one or more consumer units process the plurality of partitions in the target order.
Reconfigurable Parallel Processing
Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) that each may comprise a configuration buffer, a sequencer coupled to the configuration buffer of each of the plurality of PEs and configured to distribute one or more PE configurations to the plurality of PEs, and a gasket memory coupled to the plurality of PEs and being configured to store at least one PE execution result to be used by at least one of the plurality of PEs during a next PE configuration.
Method of securing devices used in the internet of things
Secure IoT devices and methods of use are disclosed herein. An example Internet-of-Things (IoT) device includes an interface for transmitting and receiving data on a network; and a chip comprising a reconfigurable hardware core configured to transmit the data using the interface. The reconfigurable hardware core is not vulnerable to malicious attacks can be used to replace a central processing unit (CPU) which is vulnerable to malicious attacks.
PROACTIVELY PERFORMING TASKS BASED ON ESTIMATING HARDWARE RECONFIGURATION TIMES
Proactively performing tasks based on estimating hardware reconfiguration times. A determination is made, prior to performing one or more reconfiguration actions to reconfigure a configuration of the computing environment, at least one estimated reconfiguration time to perform the one or more reconfiguration actions. At least one reconfiguration action of the one or more reconfiguration actions is performed, and one or more tasks are initiated prior to completing the one or more reconfiguration actions. The initiating is based on the at least one estimated reconfiguration time.