A parallel hypervisor system for virtualizing application-specific supercomputers is disclosed. The hypervisor system comprises (a) at least one software-virtual hardware pair consisting of a software application, and an application-specific virtual supercomputer for accelerating the said software application, wherein (i) The virtual supercomputer contains one or more virtual tiles; and (ii) The software application and the virtual tiles communicate among themselves with messages; (b) One or more reconfigurable physical tiles, wherein each virtual tile of each supercomputer can be implemented on at least one physical tile, by configuring the physical tile to perform the virtual tile's function; and (c) A scheduler implemented substantially in hardware, for parallel pre-emptive scheduling of the virtual tiles on the physical tiles.

The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

Systems and methods are disclosed herein that relate to partially reconfiguring a Field Programmable Gate Array (FPGA) of a wireless communication device to provide time-slicing of modem and application functionality. In this manner, a low-cost, small size, and low power consumption implementation of the FPGA and thus the wireless communication device is provided.

Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes performing a read operation on a non-volatile memory to obtain a first value. The method further includes comparing the value to a predetermined value to obtain a comparison result. The method further includes determining whether a boot image stored on the non-volatile memory is to be read based at least on the first comparison result. The method further includes performing, based on the determining, a read operation on the boot image to obtain data associated with booting of a device. The method further includes booting the device based at least on the data. Related systems and devices are provided.

A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.

A setting to be applied at a docking station is obtained, either from a memory of the docking station, or from another device connected to a network by first obtaining, from a user device connected to the docking station, an identity of the user device and/or an identity of a user of the user device. Based on the identity of the user and/or the user device, a configuration set, of a plurality of configuration sets, that identifies at least one setting to be applied at the docking station is obtained and a setting to apply at the docking station is determined based at least partly on the configuration set. The docking station may store a set of docking station specific settings which can be used in conjunction with the setting(s) determined from the configuration set.

The technology disclosed relates to inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor and a second reconfigurable processor. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second reconfigurable processor using one or more SmartNIC buffers.

A method of processing partitions of a tensor in a target order includes receiving, by a reorder unit and from two or more producer units, a plurality of partitions of a tensor in a first order that is different from the target order, storing the plurality of partitions in the reorder unit, and providing, from the reorder unit, the plurality of partitions in the target order to one or more consumer units. In an example, the one or more consumer units process the plurality of partitions in the target order.

An optimized reconfiguration algorithm based on dynamic voltage and frequency scaling (DVFS) is provided, which mainly has the following contributions. The optimized reconfiguration algorithm based on DVFS proposes a DVFS-based reconfiguration method, which schedules user tasks according to a degree of parallelism (DOP) of the user tasks so as to reconfigure more parallel user tasks, thereby achieving higher reliability. The optimized reconfiguration algorithm based on DVFS proposes a K-means-based heuristic approximation algorithm, which minimizes the delay of the DVFS-based reconfiguration scheduling algorithm. The optimized reconfiguration algorithm based on DVFS proposes a K-means-based method, which reduces memory overhead caused by DVFS-based reconfiguration scheduling. The optimized reconfiguration algorithm based on DVFS improves the reliability of a field programmable gate array (FPGA) system and minimizes the area overhead of a hardware circuit.

A field programmable gate array (FPGA) dynamic reconfiguration method, apparatus, device and readable storage medium are provided. The technical solution includes: performing board support package (BSP) flat compilation on a target project to obtain a static region; performing BSP generation and reconfiguration information compilation on the target project to obtain static information; revising the static region using the static information to obtain reconfiguration compilation version projects that meet timing and correspond to different reconfiguration compilation parameters, respectively; importing a preset heterogeneous acceleration kernel to the reconfiguration compilation version projects and then performing static compilation to obtain clock frequencies corresponding to the reconfiguration compilation version projects, respectively; and determining a target reconfiguration compilation version project with a clock frequency meeting performance requirements using the clock frequencies, and obtaining a dynamic reconfiguration compilation version project file. The dynamic reconfiguration compilation version project file obtained in this technical solution ensures that the static region can meet the timing, and also enables an operating clock of the heterogeneous acceleration kernel to meet the performance requirements for heterogeneous acceleration.