A system for assigning a workload to compute resources includes an interface and a processor. The interface is configured to receive a workload. The processor is configured to break the workload into a set of subproblems; and for a subproblem of the set of subproblems: determine whether the subproblem benefits from intersheet parallelism; determine whether the subproblem benefits from intrasheet parallelism; determine whether the subproblem benefits from directed acyclic graph (DAG) partitioning; and assign the subproblem, wherein assigning the subproblem utilizes optimization when appropriate based at least in part on benefits from the intersheet parallelism, the intrasheet parallelism, and the DAG partitioning.

A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). The first die does not comprise the off-die peripheral-circuit component. The first and second dice are communicatively coupled by a plurality of inter-die connections. The preferred discrete 3-D processor can be applied to mathematical computing, computer simulation, configurable gate array, pattern processing and neural network.

A method of performing unsupervised clustering of data points includes determining a number of qubits to include in a quantum processor based on feature dimensions of each data point. The method includes, for each pair of data points, executing a quantum circuit on a quantum processor having the determined number of qubits. The quantum circuit includes a feature map template circuit parameterized with a first plurality of rotations, a backward feature map template circuit parameterized with a second plurality of rotations, and a measurement circuit that outputs a similarity measure. The method includes creating a similarity matrix based on the similarity measure for each pair of data points, and inputting the similarity matrix to a classical clustering algorithm to cluster the data points. The feature map template circuit and the backward feature map template circuit each use quantum properties of superposition and entanglement of the qubits of the quantum processor.

Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.

A three-dimensional processor (3D-processor) for calculating mathematical functions in parallel, comprises a larger number (e.g. at least one thousand) of computing elements, with each computing element comprising at least one three-dimensional memory (3D-M) array for storing at least a portion of a look-up table (LUT) for a mathematical function and an arithmetic logic circuit (ALC) for performing arithmetic operations on the LUT data. Even though each individual 3D-M cell is slower than a conventional two-dimensional memory (2D-M) cell, this deficiency in speed is offset by a significantly larger scale of parallelism.

Techniques and a system for visualization or interaction with a quantum processor are provided. In one example, a system includes a quantum programming component and a visualization component. The quantum programming component manages a quantum programming process to generate topology data for a quantum processor that is indicative of a physical topology of a set of qubits associated with the quantum processor. The visualization component generates visualization data for the topology data that comprises a set of planar slice elements arranged to correspond to the physical topology of the set of qubits. The set of planar slice elements indicate one or more operations performed at a time step associated with the quantum programming process.

An array of processing elements are arranged in a three-dimensional array. Each of the processing elements includes or is coupled to a dedicated memory. The processing elements of the array are intercoupled to their nearest neighbor processing elements. A processing element on a first die may be intercoupled to a first processing element on a second die that is located directly above the processing element, a second processing element on a third die that is located directly below the processing element, and the four adjacent processing elements on the first die. This intercoupling allows data to flow from processing element to processing element in the three directions. These dataflows are reconfigurable so that they may be optimized for the task. The data flows of the array may be configured into one or more loops that periodically recycle data in order to accomplish different parts of a calculation.

A discrete three-dimensional (3-D) processor comprises a plurality of storage-processing units (SPU's), each of the SPU's comprising a non-memory circuit, at least a memory array and at least an off-die peripheral-circuit component thereof. The 3-D processor further comprises first and second dice. The first die comprises the memory arrays, whereas the second die comprises the non-memory circuit and the off-die peripheral-circuit component.

A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). The first die does not comprise the off-die peripheral-circuit component. The first and second dice are communicatively coupled by a plurality of inter-die connections. The preferred discrete 3-D processor can be applied to mathematical computing, computer simulation, configurable gate array, pattern processing and neural network.

A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.