A processor including a first vector register for storing a plurality of source data elements, a second vector register for storing a plurality of control elements, and a vector bit shuffle logic. Each of the control elements in the first vector register corresponds to a different source data element and includes a plurality of bit fields. Each of the bit fields is associated with a single corresponding bit position in a destination mask register and identifies a single bit from the corresponding source data element to be copied to the single corresponding bit position in the destination mask register. The vector bit shuffle logic is to read the bit fields from the second vector register and, for each bit field, to identify a single bit from a single corresponding source data element and copy it to a single corresponding bit position in the destination mask register.

Disclosed herein are vector index registers in vector processors that each store multiple addresses for accessing multiple positions in vectors. It is known to use scalar index registers in vector processors to access multiple positions of vectors by changing the scalar index registers in vector operations. By using a vector indexing register for indexing positions of one or more operand vectors, the scalar index register can be replaced and at least the continual changing of the scalar index register can be avoided.

Providing matrix multiplication using vector registers in processor-based devices is disclosed. In one aspect, a method for providing matrix multiplication comprises rearranging elements of a first submatrix and a second submatrix into first and second vectors, respectively, which are stored in first and second vector registers. A matrix multiplication vector operation using the first and second vector registers as input operands is then performed to generate an output vector that is stored in an output vector register. Each element E of the output vector, where 0E<R.sub.AC.sub.B, is calculated as a dot product of a plurality of elements of the first vector corresponding to a row of the first submatrix, and a plurality of elements of the second vector corresponding to a column of the second submatrix.

Aspects for generating a dot product for two vectors in neural network are described herein. The aspects may include a controller unit configured to receive a vector load instruction that includes a first address of a first vector and a length of the first vector. The aspects may further include a direct memory access unit configured to retrieve the first vector from a storage device based on the first address of the first vector. Further still, the aspects may include a caching unit configured to store the first vector.

Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a vector, wherein the vector includes one or more elements. The aspects may further include a computation module that includes one or more comparers configured to compare the one or more elements to generate an output result that satisfies a predetermined condition included in an instruction.

Aspects for vector combination in neural network are described herein. The aspects may include a direct memory access unit configured to receive aa first vector, a second vector, and a controller vector. The first vector, the second vector, and the controller vector may each include one or more elements indexed in accordance with a same one-dimensional data structure. The aspects may further include a computation module configured to select one of the one or more control values, determine that the selected control value satisfies a predetermined condition, and select one of the one or more first elements that corresponds to the selected control value in the one-dimensional data structure as an output element based on a determination that the selected control value satisfies the predetermined condition.

A system for reducing non-linearity in mixed signal processing using complex polynomial vector processor 102 is provided. The complex polynomial vector processor 102 includes a data processing unit (104) and a co-efficient feeder unit (106). The data processing unit (104) converts a high-speed data stream into a polar-like format (PL) data and calculates required polynomial powers for the high-speed data stream using the PL format data. The data processing unit (104) includes a multiplier accumulator (MAC) unit (206) that generates processed high-speed data and a delay unit (208) that combines time separated input with the processed high-speed data to generate output data with reduced non-linearity.

An apparatus and method are provided for transferring a plurality of data structures from memory into one or more vectors of data elements stored in a register bank. The apparatus has first interface circuitry to receive data structures retrieved from memory, where each data structure has an associated identifier and comprises N data elements. Multi-axial buffer circuitry is provided having an array of storage elements, where along a first axis the array is organised as N sets of storage elements, each set containing a plurality VL of storage elements, and where along a second axis the array is organised as groups of N storage elements, with each group containing a storage element from each of the N sets. Access control circuitry then stores the N data elements of a received data structure in one of the groups selected in dependence on the associated identifier. Responsive to an indication that all required data structures have been stored in the multi-axial buffer circuitry, second interface circuitry then outputs the data elements stored in one or more of the sets of storage elements as one or more corresponding vectors of data elements for storage in a register bank, each vector containing VL data elements. Such an approach can significantly increase the performance of handling such load operations, and give rise to potential energy savings.

A method of clearing of registers and logic designs with AND and OR logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.

Methods and apparatuses for determining set-membership using Single Instruction Multiple Data (SIMD) architecture are presented herein. Specifically, methods and apparatuses are discussed for determining, in parallel, whether multiple values in a first set of values are members of a second set of values. Many of the methods and systems discussed herein are applied to determining whether one or more rows in a dictionary-encoded column of a database table satisfy one or more conditions based on the dictionary-encoded column. However, the methods and systems discussed herein may apply to many applications executed on a SIMD processor using set-membership tests.