A system and method for real-time attestation which attests to the untouchability of processors from external influences. The system and method comprise a security mechanism that extracts information about a program's full-control execution path and then validates that information with a highly isolated guard process during runtime, which is running in a trusted environment. This trusted guard application also acts as a remote attester client and sends the currently running control flow graph to a remote attestator server on demand.

A method is described including selecting an impedance threshold for a battery in electrical communication with an integrated circuit; acquiring an impedance of the battery; calculating an average impedance of the battery for a period of time; determining whether the integrated circuit is a victim of a power side channel attack if the average impedance of the battery for the period of time exceeds the impedance threshold; and responding to the power side channel attack.

Detecting voltage-based attacks on an integrated circuit (IC) is difficult in the presence of clock jitter. Propagating signals can exhibit a total delay that is due to a delay component resulting from a voltage-based attack and a delay characteristic resulting from clock fluctuation. Voltage-variation detection circuitry includes first and second voltage-dependent circuits and a voltage analysis circuit. The voltage-dependent circuits produce first and second signals that are indicative of a voltage level responsive to a clock signal and based on different first and second voltage sensitivities. The voltage analysis circuit generates a voltage alert signal based on the first and second signals. A combined signal neutralizes the delay characteristic in the first and second signals, but the delay component due to the voltage variation can be at least partially maintained. Thus, a voltage-based attack is detectable in the presence of clock fluctuation by using two voltage-dependent circuits.

A device, method, or computer program product for conducting a cryptographic operation in a vehicle is disclosed herein. The device is arranged to receive key data and input data, and to conduct a cryptographic computation of the input data to output data using the key data. The cryptographic computation is conducted with or without side channel attack counter measures, which are toggled based on the key data or based on a control input.

An integrated-circuit radio transmitter chip comprises a transmitter, a cryptographic engine and control circuitry for the cryptographic engine. The cryptographic engine performs a cryptographic operation by receiving input data, performing a first process to generate first result data and a second process to generate second result data. The first and second result data are used to generate output data. In response to determining that the transmitter is active, the control circuity controls the cryptographic engine to perform the first process and prevents the cryptographic engine from performing the second process while the transmitter is active. The control circuitry controls the cryptographic engine to perform the second process in response to determining that the transmitter is not active.

Disclosed are an apparatus for detecting a cache side-channel attack which is capable of quickly detecting the cache side-channel attack in real time with high accuracy and a method thereof. The apparatus for detecting the cache side-channel attack may include a data collection unit that collects data from at least one of a core, an L1 cache, an L2 cache, and an L3 cache, respectively, and a data collection unit that collects data from at least one of a core, an L1 cache, an L2 cache, and an L3 cache, respectively.

A system includes a motherboard configured to hold electronic devices and allow communication between one or more of the electronic devices, a power supply module configured to supply power to the one or more electronic devices, a peripheral device communicatively coupled to the motherboard using a peripheral port of the motherboard to perform at least one action related to an Automated Teller Machine (ATM), and a monitoring device communicatively coupled to the motherboard. The monitoring device is configured to monitor a voltage associated with the peripheral device and detect when the monitored voltage does not match an expected voltage associated with the peripheral device. In response to the detecting, the monitoring device determines that an unauthorized activity associated with the peripheral device has occurred.

A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

Detecting voltage-based attacks on an integrated circuit (IC) is difficult in the presence of clock jitter. Propagating signals can exhibit a total delay that is due to a delay component resulting from a voltage-based attack and a delay characteristic resulting from clock fluctuation. Voltage-variation detection circuitry includes first and second voltage-dependent circuits and a voltage analysis circuit. The voltage-dependent circuits produce first and second signals that are indicative of a voltage level responsive to a clock signal and based on different first and second voltage sensitivities. The voltage analysis circuit generates a voltage alert signal based on the first and second signals. A combined signal neutralizes the delay characteristic in the first and second signals, but the delay component due to the voltage variation can be at least partially maintained. Thus, a voltage-based attack is detectable in the presence of clock fluctuation by using two voltage-dependent circuits.

The present disclosure relates to a cryptographic method comprising: multiplying a point belonging to a mathematical set with a group structure by a scalar by performing: the division of a scalar into a plurality of groups formed of a same number w of digits, w being greater than or equal to 2; and the execution, by a cryptographic circuit and for each group of digits, of a sequence of operations on point, the sequence of operations being identical for each group of digits, at least one of the operations executed for each of the groups of digits being a dummy operation.