The present application discloses an OPC model simulation method. The method includes the following steps: step 1, establishing a precision judgment function which is formed by multiplying each square of the difference between a simulation point of an OPC model and an actual point on a wafer, by weight, and then superposing all the squares; step 2, performing random data sampling, comprising forming distributed computing nodes; randomly distributing data to each computing node, and meanwhile distributing a current state value of fitting parameter space composed of all fitting parameters to each computing node; computing a local precision judgment function of each computing node; step 3, performing parallel computing to obtain the gradient of each local precision judgment function, and computing a first derivative and a first order approximate value of the gradient of each local precision judgment function; step 4, performing gradient composition and iteration.

The present application discloses an OPC model simulation method. The method includes the following steps: step 1, establishing a precision judgment function which is formed by multiplying each square of the difference between a simulation point of an OPC model and an actual point on a wafer, by weight, and then superposing all the squares; step 2, performing random data sampling, comprising forming distributed computing nodes; randomly distributing data to each computing node, and meanwhile distributing a current state value of fitting parameter space composed of all fitting parameters to each computing node; computing a local precision judgment function of each computing node; step 3, performing parallel computing to obtain the gradient of each local precision judgment function, and computing a first derivative and a first order approximate value of the gradient of each local precision judgment function; step 4, performing gradient composition and iteration.

The present disclosure provides systems and methods for scalable and parallel computation of hierarchical cascading in finite element method (FEM) simulations of surface acoustic wave (SAW) devices. Different computing units of a cluster or cloud service may be assigned to independently model different core blocks or combinations of core blocks for iterative cascading to generate a model of the SAW devices. Similarly, frequency ranges may independently be assigned to computing units for modeling and analysis of devices, drastically speeding up computation.

The present disclosure provides systems and methods for scalable and parallel computation of hierarchical cascading in finite element method (FEM) simulations of surface acoustic wave (SAW) devices. Different computing units of a cluster or cloud service may be assigned to independently model different core blocks or combinations of core blocks for iterative cascading to generate a model of the SAW devices. Similarly, frequency ranges may independently be assigned to computing units for modeling and analysis of devices, drastically speeding up computation.

Embodiments are for auto generation of a debug trace in pre-silicon verification. A configuration file is created that includes fail information of a fail related to at least one failed interface of a design. A Boolean expression is generated to represent interface signals of the at least one failed interface, the configuration file comprising the interface signals of the least one failed interface. Responsive to determining that the Boolean expression meets a condition for complexity of the Boolean expression, code is automatically generated related to the fail based on the configuration file in preparation for a simulation of the failed interface in the design. A simulation of the design is run based at least in part on the code to generate a debug trace for the fail of the at least one failed interface.

Embodiments are for auto generation of a debug trace in pre-silicon verification. A configuration file is created that includes fail information of a fail related to at least one failed interface of a design. A Boolean expression is generated to represent interface signals of the at least one failed interface, the configuration file comprising the interface signals of the least one failed interface. Responsive to determining that the Boolean expression meets a condition for complexity of the Boolean expression, code is automatically generated related to the fail based on the configuration file in preparation for a simulation of the failed interface in the design. A simulation of the design is run based at least in part on the code to generate a debug trace for the fail of the at least one failed interface.

A layout geometry of a lithographic mask is received. The layout geometry is partitioned into feature images, for example as selected from a library. The library contains predefined feature images and their corresponding precalculated mask 3D (M3D) filters. The M3D filter for a feature image represents the electromagnetic scattering effect of that feature image for a given source illumination. The mask function contribution from each of the feature images is calculated by convolving the feature image with its corresponding M3D filter. The mask function contributions are combined to determine a mask function for the lithographic mask illuminated by the source illumination.

A layout geometry of a lithographic mask is received. The layout geometry is partitioned into feature images, for example as selected from a library. The library contains predefined feature images and their corresponding precalculated mask 3D (M3D) filters. The M3D filter for a feature image represents the electromagnetic scattering effect of that feature image for a given source illumination. The mask function contribution from each of the feature images is calculated by convolving the feature image with its corresponding M3D filter. The mask function contributions are combined to determine a mask function for the lithographic mask illuminated by the source illumination.

Techniques are disclosed for eliminating redundancy in fault simulations to improve efficiency and to reduce the time and computing power required to generate a robust fault list, which results in adequate diagnostic coverage of a particular post-silicon electronic device for functional safety applications. The techniques described herein implement an automated methodology to identify identical sub-circuits in a design after the design is synthesized to gates, and utilize isomorphism to define a manner in which identical blocks may be reliably identified to ensure adequate coverage and accurate, consistent fault injection results. The netlist may advantageously implement a “flat” as opposed to a hierarchal design. Moreover, multiple levels of granularity may be identified for the various sub-circuits associated with the reference graphs used to identify isomorphic sub-graphs.

Techniques are disclosed for eliminating redundancy in fault simulations to improve efficiency and to reduce the time and computing power required to generate a robust fault list, which results in adequate diagnostic coverage of a particular post-silicon electronic device for functional safety applications. The techniques described herein implement an automated methodology to identify identical sub-circuits in a design after the design is synthesized to gates, and utilize isomorphism to define a manner in which identical blocks may be reliably identified to ensure adequate coverage and accurate, consistent fault injection results. The netlist may advantageously implement a “flat” as opposed to a hierarchal design. Moreover, multiple levels of granularity may be identified for the various sub-circuits associated with the reference graphs used to identify isomorphic sub-graphs.