The multi-agent simulation system includes a plurality of agent simulators provided for each of a plurality of agents and a center controller. The plurality of agent simulators simulate a state of each of the plurality of agents while causing the plurality of agents to interact with each other by exchange of messages. The center controller relays transmission and reception of messages between the plurality of agent simulators. The plurality of agents include a plurality of types of agents including types having different time granularity. Each of the plurality of agent simulators transmits a message to the center controller at a transmission time interval corresponding to time granularity of a target agent to be simulated.

A system for a first digitally controlled grounded inductor simulation circuit may include an OP-AMP, a digitally controlled current amplifier (DCCA), a voltage buffer, two resistors, and a capacitor. The first digitally controlled grounded inductor simulation circuit allows adjustment of an equivalent inductance value (CR.sub.1R.sub.2/A) through programming a digitally controlled current gain (A) of the DCCA. A system for a second digitally controlled grounded inductor simulation circuit includes an OP-AMP, a digitally controlled current amplifier (DCCA), a dual output current follower (CF), an active current division network (CDN), two resistors, and a capacitor. The second digitally controlled grounded inductor simulation circuit allows adjustment of an equivalent inductance value (CR.sub.1R.sub.2/αA) via programming the active CDN and the DCCA.

A system for a first digitally controlled grounded inductor simulation circuit may include an OP-AMP, a digitally controlled current amplifier (DCCA), a voltage buffer, two resistors, and a capacitor. The first digitally controlled grounded inductor simulation circuit allows adjustment of an equivalent inductance value (CR.sub.1R.sub.2/A) through programming a digitally controlled current gain (A) of the DCCA. A system for a second digitally controlled grounded inductor simulation circuit includes an OP-AMP, a digitally controlled current amplifier (DCCA), a dual output current follower (CF), an active current division network (CDN), two resistors, and a capacitor. The second digitally controlled grounded inductor simulation circuit allows adjustment of an equivalent inductance value (CR.sub.1R.sub.2/αA) via programming the active CDN and the DCCA.

System analysis by receiving a model of a complex system design. The model includes at least one layer. The analysis includes performing a plurality of simulations of the performance of the layer. The number of simulations is determined according to a number of system components associated with the layer. The analysis further includes determining a worst-case result for a set of simulations from the plurality of simulations and assigning the worst-case result to an overall system simulation.

The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: generating, by an Universal Verification Methodology test instance, constrained random parameters and random controls, and storing them to a storage area of a bus function model unit; reading, by a software test instance, the random parameters and the random controls through the central processing unit, and configuring a test of the system on chip; storing execution status information of the software test instance in the storage area; reading, by the Universal Verification Methodology test instance, the execution status information, and adjusting constraint condition for generating random parameters and random controls based on the execution status information to exclude having been tested scenarios, and converting the execution status information into coverage data for coverage analysis.

The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: generating, by an Universal Verification Methodology test instance, constrained random parameters and random controls, and storing them to a storage area of a bus function model unit; reading, by a software test instance, the random parameters and the random controls through the central processing unit, and configuring a test of the system on chip; storing execution status information of the software test instance in the storage area; reading, by the Universal Verification Methodology test instance, the execution status information, and adjusting constraint condition for generating random parameters and random controls based on the execution status information to exclude having been tested scenarios, and converting the execution status information into coverage data for coverage analysis.

Methods, machine readable media and systems for performing side channel analysis are described. In one embodiment, a method, performed on a data processing system, can receive input data that contains an RTL representation of a design of a circuit and then determine, from the input data, a set of registers that store security related data during operation of the circuit, wherein the set of registers are a subset of all of the registers in the design. The method then determines, in a simulation of power consumption of the set of registers in the RTL representation, security metrics that indicate a level of potential leakage of security related data such as secret or private cryptographic keys.

Methods, machine readable media and systems for performing side channel analysis are described. In one embodiment, a method, performed on a data processing system, can receive input data that contains an RTL representation of a design of a circuit and then determine, from the input data, a set of registers that store security related data during operation of the circuit, wherein the set of registers are a subset of all of the registers in the design. The method then determines, in a simulation of power consumption of the set of registers in the RTL representation, security metrics that indicate a level of potential leakage of security related data such as secret or private cryptographic keys.

A computing system (100) having a storage system that includes a storage device (130) and a host device (105), where the host device (105) is configured to issue memory access commands to the storage device (130). The computing system (100) further includes a prediction system (190) comprising processing circuitry that is configured to perform operations that cause the prediction system (190) to identify one or more components of the storage system (918) that limit random rad performance of the storage system (918). The operations further cause the prediction system (190) to obtain characterization data that is indicative of the impact of the one or more components on random read performance and generate a model based on the characterization data to predict random read performance of the storage system (918). The operations additionally cause the prediction system (190) to execute the model in a simulation of the storage system (918) to generate a random read performance parameter for the storage system (918).

The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: constructing a simulation verification environment for the system on chip; creating a bus function model unit, and binding the bus function model unit to the same interface at which a central processing unit being connected to the bus; creating an Universal Verification Methodology test instance, and performing the Universal Verification Methodology test instance by the bus function model unit to implement the system on chip test; creating a plurality of software test instances; and compiling the software test instances, and performing the compiled software test instances by the central processing unit to implement the system on chip test.