The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: constructing a simulation verification environment for the system on chip; creating a bus function model unit, and binding the bus function model unit to the same interface at which a central processing unit being connected to the bus; creating an Universal Verification Methodology test instance, and performing the Universal Verification Methodology test instance by the bus function model unit to implement the system on chip test; creating a plurality of software test instances; and compiling the software test instances, and performing the compiled software test instances by the central processing unit to implement the system on chip test.

Methods, systems, and computer programs are presented for determining the recipe for manufacturing a semiconductor with the use of machine learning (ML) to accelerate the definition of recipes. One general aspect includes a method that includes an operation for performing experiments for processing a component, each experiment controlled by a recipe, from a set of recipes, that identifies parameters for manufacturing equipment. The method further includes an operation for performing virtual simulations for processing the component, each simulation controlled by one recipe from the set of recipes. An ML model is obtained by training an ML algorithm using experiment results and virtual results from the virtual simulations. The method further includes operations for receiving specifications for a desired processing of the component, and creating, by the ML model, a new recipe for processing the component based on the specifications.

Methods, systems, and computer programs are presented for determining the recipe for manufacturing a semiconductor with the use of machine learning (ML) to accelerate the definition of recipes. One general aspect includes a method that includes an operation for performing experiments for processing a component, each experiment controlled by a recipe, from a set of recipes, that identifies parameters for manufacturing equipment. The method further includes an operation for performing virtual simulations for processing the component, each simulation controlled by one recipe from the set of recipes. An ML model is obtained by training an ML algorithm using experiment results and virtual results from the virtual simulations. The method further includes operations for receiving specifications for a desired processing of the component, and creating, by the ML model, a new recipe for processing the component based on the specifications.

Provided is acquiring communication information via communication or directly from an engineering DB (corresponding to one example “database”) in which the communication information related to communication devices constituting a plant network is defined; storing the acquired communication information; calculating, based on the stored communication information, a total communication amount of each of the communication devices supposed in communication executed in corresponding one of the communication devices; estimating, based on the total communication amount, an actual communication amount of each of the communication devices according to an arbitrary estimation condition specified by a user; determining at least presence/absence of a communication device whose actual communication amount exceeds communication capability of the communication device; and outputting a determined determination result to the user.

A method includes acquiring a vector data signal associated with a circuit design, performing a timing update to determine timing information for the circuit design, and identifying a glitch in the circuit design based on a shifted vector waveform. The timing information includes a signal delay associated with a cell of the circuit design. The shifted vector waveform is generated by shifting the vector data signal based on the timing information.

The present invention discloses a method for viewing simulation signals of digital products and a simulation system, the method includes: when performing FPGA simulation on digital products, reading out all external port status data of digital products in real time and recording, meanwhile reading out all internal status data of digital products once every interval time and recording; after completing the simulation, when needing a back trace to check the data of digital products in a certain clock cycle, reading out the internal status data of digital products stored at the last time point before this clock cycle and the external port status data at said time point in the recorded simulation data; and taking the read-out data as an initial status data of the FPGA, then reading out all internal status data of digital products clock by clock until running to the clock cycle that needs to be viewed.

The present invention discloses a method for viewing simulation signals of digital products and a simulation system, the method includes: when performing FPGA simulation on digital products, reading out all external port status data of digital products in real time and recording, meanwhile reading out all internal status data of digital products once every interval time and recording; after completing the simulation, when needing a back trace to check the data of digital products in a certain clock cycle, reading out the internal status data of digital products stored at the last time point before this clock cycle and the external port status data at said time point in the recorded simulation data; and taking the read-out data as an initial status data of the FPGA, then reading out all internal status data of digital products clock by clock until running to the clock cycle that needs to be viewed.

A system and method allows resimulation of a portion of a model of an electronic circuit. The system and model may predict and cache data associated with the resimulation of the portion (e.g., the initial state and input signals associated with the portion) in a computer memory. If a request is received to resimulation the portion, the system and method may use the cached data to perform the resimulation.

A system and method allows resimulation of a portion of a model of an electronic circuit. The system and model may predict and cache data associated with the resimulation of the portion (e.g., the initial state and input signals associated with the portion) in a computer memory. If a request is received to resimulation the portion, the system and method may use the cached data to perform the resimulation.

A core simulator includes one or more simulated processors, a trace-based traffic generator, and a simulated memory subsystem. Each simulated processor includes a core element and at least one lower-level cache excluded from the core element. The trace-based traffic generator includes a plurality of modeled caches that model the at least lower-level cache without modeling the core element. The trace-based traffic generator is configured to receive at least one workload trace and based on the workload trace simulate actual memory traffic to be processed by the simulated memory subsystem. The simulated memory subsystem is shared between the at least one simulated processor and the trace-based traffic generator. The trace-based traffic generator performs a data exchange with the memory subsystem based on the at least one workload trace. The data exchange impacts a measured performance of the at least one simulated processor.