A system and method transforms a model of electronic circuit to improve simulation speed and/or reduce emulation area. The model may include storage elements; one or more of these storage elements may be represented by dense memory, and the storage elements may be represented by references thereto.

A system and method transforms a model of electronic circuit to improve simulation speed and/or reduce emulation area. The model may include storage elements; one or more of these storage elements may be represented by dense memory, and the storage elements may be represented by references thereto.

A method includes receiving one or more input Artificial Intelligence (AI) networks, transforming the AI networks into respective graphs including interconnected logical operators, and mapping the graphs onto a design of a hardware accelerator including a plurality interconnected hardware engines. A performance of running the AI networks on the design of the hardware accelerator is simulated using a petri-net simulation.

Embodiments are provided to simulate a quantum circuit. A system receives a quantum circuit (or its representation), generates a graph, and adds edges for each n-qubit of fusion to be applied. Costs are estimated or calculated for various paths of gate fusion between endpoints in the graph. One or more paths are selected, for example, the lowest cost path based on a Dijkstra algorithm evaluation. A unitary matrix for each gate fusion is then generated for simulating the quantum circuit. A simulation is performed locally or remotely based on the gate fusions along the selected one or more paths, and thus, improving the memory and processor performance of the simulation.

A method for analyzing a simulation of the execution of a quantum circuit includes: a step of post-selecting one or more particular values of one or more qubits at one or more steps of the simulation; a step of setting filtration that sets the value of one or more quantum states of the quantum state vector(s) derived from the post-selection(s) of qubits; a step of analyzing the part of the simulation that corresponds to the post-selection(s) of qubits and to the quantum state vector(s) filtered.

A method for analyzing a simulation of the execution of a quantum circuit includes: a step of post-selecting one or more particular values of one or more qubits at one or more steps of the simulation; a step of setting filtration that sets the value of one or more quantum states of the quantum state vector(s) derived from the post-selection(s) of qubits; a step of analyzing the part of the simulation that corresponds to the post-selection(s) of qubits and to the quantum state vector(s) filtered.

A computer-implemented method is provided for reducing a measure time of a measure process in a multi-shot simulation performed by a quantum computing simulation system. The method includes calculating probabilities from probability amplitudes before the measure process. The method further includes creating, for each node of the quantum computing simulation system, an index of probability by incrementally summing respective different ones of the probabilities into respective sums. The method also includes generating a random number for each of the multi-shots, the random number for sampling a probability distribution of the probabilities. The method additionally includes selecting the index of probability which is larger than the random number by comparing the random number generated for a given one of the multi-shots to the index of probability created for the given one of the multi-shots.

A system is provided to validate a computer processor. The system includes a computing system configured to obtain core dump data including executable instructions corresponding to a code stored in a legacy processor. An instruction-level simulator is installed in the computing system and is configured to simulate the executable instructions to generate a plurality of instruction traces. The system further includes a pre-silicon chip model simulator configured to execute the instruction traces to generate performance data. The computer processor is verified based at least in part on the performance data.

A system is provided to validate a computer processor. The system includes a computing system configured to obtain core dump data including executable instructions corresponding to a code stored in a legacy processor. An instruction-level simulator is installed in the computing system and is configured to simulate the executable instructions to generate a plurality of instruction traces. The system further includes a pre-silicon chip model simulator configured to execute the instruction traces to generate performance data. The computer processor is verified based at least in part on the performance data.

A system displays a visual representation of the operation of an electronic circuit. The position of graphical elements representing values of signals in the circuit convey information about the operation of the circuit. The visual representation may further depict navigable levels of hierarchy of the electronic circuit.