A system receives a specification of a circuit design for performing simulation of the circuit design. The specification includes one or more prototyping statements. A prototyping statement is processed by simulation of the circuit design. The system generates a netlist graph based on the specification of the circuit design. The system ignores the prototyping statements while generating the netlist graph. The system modifies the netlist graph to incorporate the prototyping statements of the specification. The netlist graph is modified by adding at least a net to the netlist graph based on a prototyping statement. The system performs static analysis based on the modified netlist graph.

A system receives a specification of a circuit design for performing simulation of the circuit design. The specification includes one or more prototyping statements. A prototyping statement is processed by simulation of the circuit design. The system generates a netlist graph based on the specification of the circuit design. The system ignores the prototyping statements while generating the netlist graph. The system modifies the netlist graph to incorporate the prototyping statements of the specification. The netlist graph is modified by adding at least a net to the netlist graph based on a prototyping statement. The system performs static analysis based on the modified netlist graph.

Techniques improve integrated circuit design by employing multi-operating condition frequency prediction for statically timed designs through statistical analysis. A design management component (DMC) can determine a trained model representing timing path properties and operating conditions of agnostic timing paths based on an analysis of vectorized data that represents timing path information associated with the agnostic timing paths. DMC can perform statistical regression on the vectorized data to facilitate training the trained model. A static timing analysis (STA) component can perform STA on design information associated with the integrated circuitry design and determine an operating condition of a timing path of the integrated circuitry design based on the STA. DMC can predict or determine at least one other operating condition associated with the integrated circuitry design based on the operating condition and the trained model.

Techniques improve integrated circuit design by employing multi-operating condition frequency prediction for statically timed designs through statistical analysis. A design management component (DMC) can determine a trained model representing timing path properties and operating conditions of agnostic timing paths based on an analysis of vectorized data that represents timing path information associated with the agnostic timing paths. DMC can perform statistical regression on the vectorized data to facilitate training the trained model. A static timing analysis (STA) component can perform STA on design information associated with the integrated circuitry design and determine an operating condition of a timing path of the integrated circuitry design based on the STA. DMC can predict or determine at least one other operating condition associated with the integrated circuitry design based on the operating condition and the trained model.

A path verification method in a logic circuit includes determining a plurality of first paths that are to be tested in a design for test (DFT) mode, determining a plurality of second paths that are to be tested in a function mode, determining a third path in the plurality of first paths and the plurality of second paths that does not need to achieve optimal performance in the function mode, and setting a time sequence constraint for the third path in the function mode to cause the third path to achieve target performance within a number AA clock cycles. AA is less than or equal to a ratio of a clock frequency in the function mode to a clock frequency in the DFT mode. AA is a positive integer.

A path verification method in a logic circuit includes determining a plurality of first paths that are to be tested in a design for test (DFT) mode, determining a plurality of second paths that are to be tested in a function mode, determining a third path in the plurality of first paths and the plurality of second paths that does not need to achieve optimal performance in the function mode, and setting a time sequence constraint for the third path in the function mode to cause the third path to achieve target performance within a number AA clock cycles. AA is less than or equal to a ratio of a clock frequency in the function mode to a clock frequency in the DFT mode. AA is a positive integer.

A method of operating a computing device for detecting clock domain crossing (CDC) violation in a design of a memory device, the method includes parsing a Netlist to generate a circuit database, parsing a clock tree using the circuit database to generate a clock tree database, extracting a non-toggled point using the clock tree database to generate a false path database based on the non-toggled point, and extracting a CDC violation identified from one or more simulation waveforms using the clock tree database and the false path database.

Examples relate to an apparatus, device, method, and computer program for generating logic to be performed by computing circuitry of a computing architecture. The apparatus is configured to determine a performance-critical compute path of a compute kernel to be executed on a plurality of units of computing circuitry of a computing architecture, the compute kernel comprising a plurality of interdependent groups of computational instructions, with the performance-critical compute path being based on a subset of the interdependent groups of computational instructions. The apparatus is configured to determine, for at least one group of computational instructions outside the performance-critical compute path, a reduced clock frequency being lower than a maximally feasible clock frequency of the respective group of computational instructions. The apparatus is configured to generate logic to be performed by one or more of the plurality of separately controllable units of computing circuitry based on the compute kernel, wherein a portion of the logic that is generated to be performed by the plurality of separately controllable units of computing circuitry outside the performance-critical compute path is generated based at least in part on the reduced clock frequency.

An equivalent input characterization waveform (EICW) is determined for a channel-connected block (CCB) located on a boundary of a cell, for a specific waveform of interest. The EICW and the specific waveform of interest produce a same timing characteristic of the CCB, but the EICW belongs to a set of waveforms on which a behavioral timing model for the multi-stage cell is based whereas the specific waveform of interest is not so limited. A timing response of the multi-stage cell is then estimated based on applying the EICW.

An equivalent input characterization waveform (EICW) is determined for a channel-connected block (CCB) located on a boundary of a cell, for a specific waveform of interest. The EICW and the specific waveform of interest produce a same timing characteristic of the CCB, but the EICW belongs to a set of waveforms on which a behavioral timing model for the multi-stage cell is based whereas the specific waveform of interest is not so limited. A timing response of the multi-stage cell is then estimated based on applying the EICW.