Test line structures are provided. A test line structure includes a semiconductor substrate, a plurality of diagnosis units and a plurality of first micro pad units. The diagnosis units are formed over the semiconductor substrate. Each of the diagnosis units includes a first interconnect structure having a first routing pattern. The first interconnect structures of the diagnosis units are connected in series to form a first test chain through the first micro pad units, and each of the first micro pad units is configured to connect the first interconnect structures of two adjacent diagnosis units in the first test chain. The first routing patterns of the first interconnect structures in the diagnosis units are different.

Test line structures are provided. A test line structure includes a semiconductor substrate, a plurality of diagnosis units and a plurality of first micro pad units. The diagnosis units are formed over the semiconductor substrate. Each of the diagnosis units includes a first interconnect structure having a first routing pattern. The first interconnect structures of the diagnosis units are connected in series to form a first test chain through the first micro pad units, and each of the first micro pad units is configured to connect the first interconnect structures of two adjacent diagnosis units in the first test chain. The first routing patterns of the first interconnect structures in the diagnosis units are different.

A method of path routing in a multilayered structure including layers and one or more links formed between adjacent layers includes identifying path connection elements included in each layer of a multilayered structure with layers that can have at least one links between adjacent layers, generating, for each layer of the multilayered structure, an embedded frame including the path connection elements identified in each layer of the multilayered structure, generating a topological frame including an outer boundary enclosing one or more punctures formed by the links among the plurality of path connection elements included in the embedded frame and one or more local path points arranged on a boundary of each of the one or more punctures, and generating a circular frame including a single circular closed curve by merging the boundary of each of the one or more punctures and the outer boundary of the topological frame.

A modeling method includes the following: acquiring electrical parameters of each sub-structure in a through silicon via (TSV) structure; obtaining an electrical topology network model according to a connection relationship of each TSV structure between two dies; and obtaining a simulation model for simulation based on the electrical topology network model and the electrical parameters.

A modeling method includes the following: acquiring electrical parameters of each sub-structure in a through silicon via (TSV) structure; obtaining an electrical topology network model according to a connection relationship of each TSV structure between two dies; and obtaining a simulation model for simulation based on the electrical topology network model and the electrical parameters.

The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.

The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.

An approach includes a new power and ground structure description language (PSDL) will allow the user to describe the desired routing pattern for each layer and on a user defined region by region basis, including how the pattern will be laid out in the design with respect to other patterns from a different layer. The new PSDL also gives the complete picture of the entire power and ground structure, instead of just a layer-by-layer view from a single command. It also allowed flexibility in alignment especially when dealing with track misalignments, thus avoiding the extensive trial-and-error steps needed to calculate offsets and distances to maintain pattern alignment using previous approaches. Additionally, because PSDL is not tightly dependent on the design size and/or floorplan, transferring the desired power and ground structure from one design to another will be very easy with only few adjustments.

An approach includes a new power and ground structure description language (PSDL) will allow the user to describe the desired routing pattern for each layer and on a user defined region by region basis, including how the pattern will be laid out in the design with respect to other patterns from a different layer. The new PSDL also gives the complete picture of the entire power and ground structure, instead of just a layer-by-layer view from a single command. It also allowed flexibility in alignment especially when dealing with track misalignments, thus avoiding the extensive trial-and-error steps needed to calculate offsets and distances to maintain pattern alignment using previous approaches. Additionally, because PSDL is not tightly dependent on the design size and/or floorplan, transferring the desired power and ground structure from one design to another will be very easy with only few adjustments.

A semiconductor device including first and second standard cells disposed in one of a first direction and a second direction intersecting the first direction, the first and second directions parallel to a substrate, and each of the first and second standard cells including a gate structure and an active region, and a filler cell adjacent to the first standard cell in the second direction and adjacent to the second standard cell in the first direction, wherein an output node of the first standard cell is connected to an input node of the second standard cell, an output active contact providing an output node of the first standard cell is connected to a wiring active contact among at least one dummy active contact included in the filler cell, and an input wiring providing an input node of the second standard cell is connected to the wiring active contact may be provided.