A system and method for automatically generating placement of vias within redistribution layers of a semiconductor package are described. In various implementations, a user defines attributes to use for automatic via generation in redistribution layers of a semiconductor package. The circuitry of a processor of a computing device used by the user executes instructions of an automatic redistribution layer (RDL) via generator. The automatic via generator uses the attributes, data indicative of the RDL netlist of signal routes within the RDL, and RDL mask layout data representing the signal masks of the metal layers within the RDL. The processor generates placement of vias for in the RDL based on the attributes and an identification of overlapping regions between metal layers.

A system and method for automatically generating placement of vias within redistribution layers of a semiconductor package are described. In various implementations, a user defines attributes to use for automatic via generation in redistribution layers of a semiconductor package. The circuitry of a processor of a computing device used by the user executes instructions of an automatic redistribution layer (RDL) via generator. The automatic via generator uses the attributes, data indicative of the RDL netlist of signal routes within the RDL, and RDL mask layout data representing the signal masks of the metal layers within the RDL. The processor generates placement of vias for in the RDL based on the attributes and an identification of overlapping regions between metal layers.

A structure includes a first package component including a first conductive pad, and a second package component overlying the first package component. The second package component includes a surface dielectric layer, and a conductive bump protruding lower than the surface dielectric layer. The first conductive bump includes a first sidewall facing away from a center of the first package component, and a second sidewall facing toward the center. A solder bump joins the first conductive pad to the first conductive bump. The solder bump contacts the first sidewall. An underfill is between the first package component and the second package component, and the underfill contacts the second sidewall.

A structure includes a first package component including a first conductive pad, and a second package component overlying the first package component. The second package component includes a surface dielectric layer, and a conductive bump protruding lower than the surface dielectric layer. The first conductive bump includes a first sidewall facing away from a center of the first package component, and a second sidewall facing toward the center. A solder bump joins the first conductive pad to the first conductive bump. The solder bump contacts the first sidewall. An underfill is between the first package component and the second package component, and the underfill contacts the second sidewall.

A robust, reliable, and efficient UHD HDR IP client device, such as a set top box, receives content, for example, from a cable service provider so that the content can be displayed to a compatible display device with improved visual effect. The UHD HDR IP client device PCB design layout comprises a PCB. The PCB includes six layers that maximize the efficiency of the UHD HDR IP client device that includes. The six layers with a design layout that maximizes efficiency and routing provides an improved quality of experience for a user for viewing on a display received 4K or higher content.

A robust, reliable, and efficient UHD HDR IP client device, such as a set top box, receives content, for example, from a cable service provider so that the content can be displayed to a compatible display device with improved visual effect. The UHD HDR IP client device PCB design layout comprises a PCB. The PCB includes six layers that maximize the efficiency of the UHD HDR IP client device that includes. The six layers with a design layout that maximizes efficiency and routing provides an improved quality of experience for a user for viewing on a display received 4K or higher content.

The present disclosure relates to routing superconducting wires in superconducting circuits and in particular to efficiently routing superconducting wires that meet inductance requirements. The superconducting wire routing technique involves modeling the target location not only as a physical location, but as a physical location (e.g., x, y, and z dimensions) combined with inductance (e.g., a target inductance range). One or more other constraints may also be included in the modeling, such as a number of wires that would need to be moved/lifted, a number of circuit-vias allowing passage through layers of the circuit, an amount of cross-coupling with other inductors, and a number of wire segments.

An integrated circuit including: a first cell including first-a and second-a output pins, a first routing wire connecting the first-a output pin to the second-a output pin, a first-a via connecting the first-a output pin to the first routing wire, and a second-a via connecting the second-a output pin to the first routing wire; and a second cell including first-b and second-b output pins, a second routing wire connecting the first-b output pin to the second-b output pin, a first-b via connecting the first-b output pin to the second routing wire, and a second-b via connecting the second-b output pin to the second routing wire, wherein the first-a via is at a first-a position, the second-a via is at a second-a position, the first-b via is at a first-b position, the second-b via is at a second-b position different from each other.

An integrated circuit including: a first cell including first-a and second-a output pins, a first routing wire connecting the first-a output pin to the second-a output pin, a first-a via connecting the first-a output pin to the first routing wire, and a second-a via connecting the second-a output pin to the first routing wire; and a second cell including first-b and second-b output pins, a second routing wire connecting the first-b output pin to the second-b output pin, a first-b via connecting the first-b output pin to the second routing wire, and a second-b via connecting the second-b output pin to the second routing wire, wherein the first-a via is at a first-a position, the second-a via is at a second-a position, the first-b via is at a first-b position, the second-b via is at a second-b position different from each other.

A method of making a back-end-of-line (BEOL) component includes filling spaces in a layer of metal material and a layer of hardmask material with a layer of scaffolding material. The method further includes forming at least one plug on top of the layer of metal material such that the at least one plug is integrally formed with the layer of scaffolding material. The method further includes removing the layer of hardmask material such that a top surface of the layer of metal material is exposed except where the at least one plug is formed on top of the layer of metal material. The method further includes recessing the layer of metal material where the top surface of the layer of metal material is exposed. The method further includes removing the scaffolding material.