A method is disclosed for creating a flattened version of a three-dimensional electrical harness assembly design in a computer-aided design environment. The method includes storing data in computer memory including route segment identifiers, diameters, lengths, and end points for route segments in the electrical harness assembly. A computer processor designates route segments as forming a trunk line of the electrical harness assembly, based on the stored data, and produces a flattened two-dimensional version of the design. All the route segments designated as forming the trunk line are represented in the flattened 2D version by straight connected lines, having a particular orientation (e.g., horizontal), and every other route segment is represented as extending out from the trunk line. The flattened 2D version is displayed on a display screen of a computer.

A method is disclosed for creating a flattened version of a three-dimensional electrical harness assembly design in a computer-aided design environment. The method includes storing data in computer memory including route segment identifiers, diameters, lengths, and end points for route segments in the electrical harness assembly. A computer processor designates route segments as forming a trunk line of the electrical harness assembly, based on the stored data, and produces a flattened two-dimensional version of the design. All the route segments designated as forming the trunk line are represented in the flattened 2D version by straight connected lines, having a particular orientation (e.g., horizontal), and every other route segment is represented as extending out from the trunk line. The flattened 2D version is displayed on a display screen of a computer.

Provided are an integrated circuit including a first standard cell including a first metal layer including a plurality of tracks respectively extending in a first horizontal direction and spaced apart from each other in a second horizontal direction, a jog pattern that includes a conductive pattern formed on a track selected from the plurality of tracks, and a connection pattern formed off the plurality of tracks, a plurality of gate lines respectively extending in the second horizontal direction, and a gate contact configured to connect a gate line selected from the plurality of gate lines to the first metal layer to connect the connection pattern to the selected gate line, and a method for fabricating the same.

Provided are an integrated circuit including a first standard cell including a first metal layer including a plurality of tracks respectively extending in a first horizontal direction and spaced apart from each other in a second horizontal direction, a jog pattern that includes a conductive pattern formed on a track selected from the plurality of tracks, and a connection pattern formed off the plurality of tracks, a plurality of gate lines respectively extending in the second horizontal direction, and a gate contact configured to connect a gate line selected from the plurality of gate lines to the first metal layer to connect the connection pattern to the selected gate line, and a method for fabricating the same.

A method for automatically creating a global routing solution for an integrated circuit. The method includes generating n original population of GR solutions. In one or more subsequent phases the method generates succeeding populations of GR solutions. The generation of each succeeding population includes determining a plurality of base GR solutions from the current population of GR solutions, determining a plurality of DRC hotspot areas within the plurality of base GR solutions, determining a plurality of patching GR solutions from which patches may be extracted, and hybridizing patching of GR solutions into base GR solutions.

A method for automatically creating a global routing solution for an integrated circuit. The method includes generating n original population of GR solutions. In one or more subsequent phases the method generates succeeding populations of GR solutions. The generation of each succeeding population includes determining a plurality of base GR solutions from the current population of GR solutions, determining a plurality of DRC hotspot areas within the plurality of base GR solutions, determining a plurality of patching GR solutions from which patches may be extracted, and hybridizing patching of GR solutions into base GR solutions.

A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; and adding at least one additional conductive pillar or at least one additional power rail in the initial power delivery network according to a relationship of a pillar density of the initial power delivery network and a maximum pillar density when the circuit design does not meet the predetermined specification.

A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; and adding at least one additional conductive pillar or at least one additional power rail in the initial power delivery network according to a relationship of a pillar density of the initial power delivery network and a maximum pillar density when the circuit design does not meet the predetermined specification.

The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes defining a layout unit for a circuit implementation and arranging multiple layout units into a layout cell. The method also includes editing the layout cell to connect a first set of the layout units to be representative of the circuit implementation and to connect a second set of the layout units to be representative of a non-functional circuit. Further, the method includes inserting one or more dummy fill structures in areas of the layout cell unoccupied by the first and second sets of layout units.

The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes defining a layout unit for a circuit implementation and arranging multiple layout units into a layout cell. The method also includes editing the layout cell to connect a first set of the layout units to be representative of the circuit implementation and to connect a second set of the layout units to be representative of a non-functional circuit. Further, the method includes inserting one or more dummy fill structures in areas of the layout cell unoccupied by the first and second sets of layout units.