A computer implemented method for converting an input computer program into an output computer program having a target global accuracy discloses, including: receiving a target internal accuracy for each mathematical function included in the input computer program, analyzing the input computer program to determine a dependency graph describing dependencies between mathematical functions calls, the mathematical functions being processed according to the dependency graph by, for each processed mathematical function: using a value range determination tool to produce a value range for the processed mathematical function based on each synthesized mathematical function obtained for a mathematical function on which the processed mathematical function depends according to the dependency graph, using a synthesis tool to produce a synthesized mathematical function having the target internal accuracy, the output computer program being generated by replacing each mathematical function call by a call to its corresponding synthesized mathematical function.

Systems, apparatuses, and methods related to a neuron using posits are described. An example apparatus may include a memory array including a plurality of memory cells configured to store data. The data can include a plurality of bit strings. The example apparatus may include a neuron component coupled to the memory array. The neuron component can include neuron circuitry configured to perform neuromorphic operations on at least one of the plurality of bit strings.

The present application is directed to determining attributes for results of arithmetic operations with fixed-point numbers. An indication is received of possible word lengths to store digits representing a result of an arithmetic operation with fixed-point numbers. An indication is received of how a placement of a radix point will be determined in the digits representing the result of the arithmetic operation with fixed-point numbers. When calculating the fixed-point arithmetic operation, one of the possible word lengths is employed for storing the digits representing the result of the fixed-point arithmetic operation. A placement of a radix point in the digits is based on the received indication of how the radix point is to be determined. Growth rate for a number of digits in a result of a series of arithmetic calculations is less than N, where N is equal to the number of arithmetic operations performed.

Disclosed is a data processing device capable of efficiently performing an arithmetic process on variable-length data and an arithmetic process on fixed-length data. The data processing device includes first PEs of SIMD type, SRAMs provided respectively for the first PEs, and second PEs. The first PEs each perform an arithmetic operation on data stored in a corresponding one of the SRAMs. The second PEs each perform an arithmetic operation on data stored in corresponding ones of the SRAMs. Therefore, the SRAMs can be shared so as to efficiently perform the arithmetic process on variable-length data and the arithmetic process on fixed-length data.

A matrix-vector multiplication device includes an input encoder that encodes an input vector into a binary complement format value and a binary true format value; a pulse generator that converts each encoded bit of the binary complement format value and each encoded bit of the binary true format value into a corresponding pulse signal; a crossbar array of weights, wherein each weight is encoded as a differential analog conductance of resistive memory devices, wherein the pulse generator simultaneously applies a pulse signal corresponding to a given encoded bit of the binary complement format value and a pulse signal corresponding to a given encoded bit of the binary true format value to corresponding resistive memory devices; an analog-to-digital converter that digitizes outputs of the crossbar array of weights to generate partial dot-product results; and a digital counter that computes a final dot-product result from the partial dot-product results.

The present disclosure relates to a computing device for processing a multi-bit width value, an integrated circuit board card, a method, and a computer readable storage medium. The computing device may be included in a combined processing apparatus, and the combined processing apparatus may further include a general interconnection interface, and an other processing device. The computing device interacts with the other processing device to jointly complete a computing operation specified by a user. The combined processing apparatus may further include a storage device connected to an apparatus and the other processing device and configured to store data of the apparatus and the other processing device. The solution of the present disclosure can split the multi-bit width value so that the processing capability of the processor is not influenced by the bit width.

A method for accelerating a convolution operation includes receiving from an I/O interface, a first data set and a second data set. Transforming the first data set into a first converted data set, the first converted data set having the first format. Transforming the second data set into a second converted data set, the second converted data set having the second format. Loading into a convolution functional unit, the first converted data set and the second converted data set, where the convolution functional unit is configured to receive a first data in a first format, to receive a second data in a second format, and to output a third data in a third format. Receiving, by the task scheduler from the convolution functional unit, a result in the third format.

An artificial intelligence (AI) calculation circuit is provided. The AI calculation circuit can support various integer and floating-point calculations through the adjustment of circuit configuration. Integer multiplication and floating-point mantissa multiplication share the multiplication unit, integer comparison and floating-point comparison share the same comparison unit, integer addition and floating-point addition share the same addition unit.