This application relates to a multi-layer convolution operation. The multi-layer convolution operation is optimized for a vector processing unit having a number of data paths configured to operate on vector operands containing a number of elements processed in parallel by the data paths. The convolution operation specifies a convolution kernel utilized to filter a multi-channel input and generate a multi-channel output of the convolution operation. A number of threads are generated to process blocks of the multi-channel output, each block comprising a set of windows of a number of channels of the multi-channel output. Each window is a portion of the array of elements in a single layer of the multi-channel output. Each thread processes a block in accordance with an arbitrary width of the block, processing a set of instructions for each sub-block of the block having a well-defined width, the instructions optimized for the vector processing unit.

Integrated circuits with digital signal processing (DSP) blocks are provided. A DSP block may include one or more large multiplier circuits. A large multiplier circuit such as an 1818 multiplier circuit may be used to support two or more smaller multiplication operations such as two 88 integer multiplications or two 99 integer multiplications. To implement the two 88 or 99 unsigned/signed multiplications, the 1818 multiplier may be configured to support two 88 multiplications with one shared operand, two 66 multiplications without any shared operand, or two 77 multiplications without any shared operand. Any potential overlap of partial product terms may be subtracted out using correction logic. The multiplication of the remaining most significant bits can be computed using associated multiplier extension logic and appended to the other least significant bits using merging logic.

Systems, apparatuses, and methods for efficiently processing arithmetic operations are disclosed. A computing system includes a processor capable of executing single precision mathematical instructions on data sizes of M bits and half precision mathematical instructions on data sizes of N bits, which is less than M bits. At least two source operands with M bits indicated by a received instruction are read from a register file. If the instruction is a packed math instruction, at least a first source operand with a size of N bits less than M bits is selected from either a high portion or a low portion of one of the at least two source operands read from the register file. The instruction includes fields storing bits, each bit indicating the high portion or the low portion of a given source operand associated with a register identifier specified elsewhere in the instruction.

Embodiments of systems, apparatuses, and methods for vector-packed fractional multiplication of signed words with rounding, saturation, and high-result selection in a processor are described. For example, execution circuitry executes a decoded instruction to perform a fractional multiplication operation for each of a plurality of pairs of packed data elements to yield a plurality of output values, round each of the plurality of output values, detect whether any of the plurality of output values reflect an overflow or underflow, for any of the plurality of output values that reflect an overflow or underflow, saturate the output value, and store the plurality of output values into a corresponding plurality of positions of the packed data destination operand.

An apparatus and method are provided for processing input operand values. The apparatus has a set of vector data storage elements, each vector data storage element providing a plurality of sections for storing data values. A plurality of lanes are considered to be provided within the set of storage elements, where each lane comprises a corresponding section from each vector data storage element. Processing circuitry is arranged to perform an arithmetic operation on an input operand value comprising a plurality of portions, by performing an independent arithmetic operation on each of the plurality of portions, in order to produce a result value comprising a plurality of result portions. Storage circuitry is arranged to store the result value within a selected lane of the plurality of lanes, such that each result portion is stored in a different vector data storage element within the corresponding section for the selected lane. Such an approach allows efficient processing of input operand values in a manner that is not constrained by the size of the vector data storage elements, and in particular in a way that is vector length agnostic.

Apparatuses, systems, and techniques to perform matrix multiply-accumulate (MMA) operations on data of a first type using one or more MMA instructions for data of a second type. In at least one embodiment, a single tensorfloat-32 (TF32) MMA instruction computes a 32-bit floating point (FP32) output using TF32 input operands converted from FP32 data values.

An apparatus and method for performing addition of signed packed data values using rotation and halving. For example, one embodiment of a processor comprises: a decoder to decode an instruction to generate a decoded instruction, the instruction including an opcode, an immediate, and operands identifying a plurality of packed data source registers and a packed data destination register a first source register to store a first plurality of packed signed words; a second source register to store a second plurality of packed signed words; execution circuitry to execute the decoded instruction, the execution circuitry comprising: adder circuitry to add each packed signed word from the first source register with a selected packed signed word from the second source register to generate a plurality of signed word results, the adder circuitry to select each packed signed word from the second source register in accordance with a rotation value in the immediate of the instruction, the rotation value to indicate an amount of rotation to be applied to the packed signed words in the second source register prior to the adder circuitry performing the adding; and a destination register to store the plurality of signed word results in specified data element locations of the destination register.

An information processing apparatus includes a memory and a processor coupled to the memory. The processor acquires statistical information including a distribution of operation result values from the memory, when it is determined that a number of acquired statistical information samples is larger than a predetermined value, generates a program by setting a data type for which a ratio of a maximum value to a minimum value of values that can be expressed is smaller among data types usable for target data in an operation as the target data, and when it is determined that the number of acquired statistical information samples is smaller than the predetermined value, generates the program by setting the data type for which the ratio of the maximum value to the minimum value of values that can be expressed is larger among data types usable for target data in the operation as the target data.

An apparatus and method down-converting and interleaving data elements. For example, one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed data elements; a second source register to store a second plurality of packed data elements; a destination register to store a third plurality and a fourth plurality of packed data elements, each of the third and fourth plurality of packed data elements to be encoded with fewer bits than each of the first and second plurality of packed data elements; execution circuitry to execute the decoded instruction, the execution circuitry comprising: down-conversion circuitry to down-convert each of the first plurality of packed data elements to generate one of the third plurality of packed data elements and to down-convert each of the second plurality of packed data elements to generate one of the fourth plurality of packed data elements; interleave circuitry to interleave the third plurality of packed data elements with the fourth plurality of packed data elements within the destination register.

An apparatus and method for performing addition of signed packed data values using rotation and halving. For example, one embodiment of a processor comprises: a decoder to decode an instruction to generate a decoded instruction, the instruction including an opcode, an immediate, and operands identifying a plurality of packed data source registers and a packed data destination register a first source register to store a first plurality of packed signed words; a second source register to store a second plurality of packed signed words; execution circuitry to execute the decoded instruction, the execution circuitry comprising: adder circuitry to add each packed signed word from the first source register with a selected packed signed word from the second source register to generate a plurality of signed word results, the adder circuitry to select each packed signed word from the second source register in accordance with a rotation value in the immediate of the instruction, the rotation value to indicate an amount of rotation to be applied to the packed signed words in the second source register prior to the adder circuitry performing the adding; and a destination register to store the plurality of signed word results in specified data element locations of the destination register.