A reference voltage buffer circuit includes an operational amplifier, a capacitor switching module, a first transistor and a second transistor. The operational amplifier includes two input terminals and an output terminal, where the two input terminals receive an input reference voltage and a feedback voltage, respectively. A gate electrode of the first transistor is coupled to the capacitor switching module, and a source electrode of the first transistor provides the feedback voltage. A gate electrode of the second transistor is coupled to the capacitor switching module, and a source electrode of the second transistor provides an output reference voltage. In addition, the operational amplifier generates a stable control voltage to the gate electrodes of the first transistor and the second transistors via the capacitor switching module while the output terminal of the operational amplifier is not directly connect to the gate electrodes of the first transistor and the second transistors.

Disclosed is a current sampling circuit including a proportional current output circuit and a full differential common mode negative feedback circuit, specifically the proportional current output circuit is configured to calculate a current output from a power device according to a preset proportion to obtain a first proportional current and a second proportional current, and to output the first proportional current and the second proportional current to the full differential common mode negative feedback circuit; and the full differential common mode negative feedback circuit is configured to shunt respectively the first proportional current and the second proportional current using a full differential common mode negative feedback network with a bias current in microamps to obtain a first sampling current and a second sampling current, and to output constantly the first sampling current and the second sampling current. Further disclosed is a current sampling method.

Devices and methods that aim to improve flicker noise rejection in switched-capacitor (SC) integrators are disclosed. An example SC integrator includes a first and a second sampling capacitors, an amplifier, an integrating capacitor, coupled at least to an output of the amplifier, and a switching arrangement. By adding (i.e., integrating in the integrating capacitor) sign-inverted samples of a flicker noise of the amplifier at every clock cycle of a master clock and by keeping the time distance/delay between those samples relatively small regardless of the master clock frequency, such a SC integrator may provide improvements in terms of rejecting the flicker noise of the amplifier.

Devices and methods that aim to improve flicker noise rejection in switched-capacitor (SC) integrators are disclosed. An example SC integrator includes a first and a second sampling capacitors, an amplifier, an integrating capacitor, coupled at least to an output of the amplifier, and a switching arrangement. By adding (i.e., integrating in the integrating capacitor) sign-inverted samples of a flicker noise of the amplifier at every clock cycle of a master clock and by keeping the time distance/delay between those samples relatively small regardless of the master clock frequency, such a SC integrator may provide improvements in terms of rejecting the flicker noise of the amplifier.

To provide a hysteresis comparator having a small circuit area and low power consumption. The hysteresis comparator includes a comparator, a switch, a first capacitor, a second capacitor, and a logic circuit. A first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator. An output terminal of the comparator is electrically connected to an input terminal of the logic circuit. An output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor. The logic circuit has a function of generating an inverted signal of a signal input to the input terminal of the logic circuit and outputting the inverted signal to the output terminal of the logic circuit. A reference potential is input to the first input terminal of the comparator and the reference potential is held by the switch. Due to change in the potential of the output terminal of the comparator, the reference potential is changed by capacitive coupling of the second capacitor.

To provide a hysteresis comparator having a small circuit area and low power consumption. The hysteresis comparator includes a comparator, a switch, a first capacitor, a second capacitor, and a logic circuit. A first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator. An output terminal of the comparator is electrically connected to an input terminal of the logic circuit. An output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor. The logic circuit has a function of generating an inverted signal of a signal input to the input terminal of the logic circuit and outputting the inverted signal to the output terminal of the logic circuit. A reference potential is input to the first input terminal of the comparator and the reference potential is held by the switch. Due to change in the potential of the output terminal of the comparator, the reference potential is changed by capacitive coupling of the second capacitor.

Numerous embodiments for processing the current output of a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The embodiments comprise a summer circuit and an activation function circuit. The summer circuit and/or the activation function circuit comprise circuit elements that can be adjusted in response to the total possible current received from the VMM to optimize power consumption.

Computing-in-memory utilizes memory as weight for multiply-and-accumulate (MAC) operations. Input data multiplies weights to produce output data during the operation. Method of data conversion from input data, memory element to output data is described to enhance the computing efficiency.

A switching regulator includes a switching element, a rectifier element, an output capacitor having one electrode connected to an output terminal, a control circuit which supplies a pulse width modulation signal in accordance with a voltage of the output terminal to a control terminal of the switching element, a load determination circuit which outputs a determination signal in accordance with a load, based on a voltage of the control terminal of the switching element, and a variable inductance circuit including a plurality of coils and having an inductance value which is switchable based on the determination signal.

A synchronous rectifier includes: an integrator configured to integrate a voltage across a secondary side winding of a transformer over an integral period having an expected zero integral value; a first comparator configured to detect an end of a demagnetization phase of the secondary side winding based on diode detection; and a digital circuit configured to adjust a channel gain of the synchronous rectifier based on an integration error at the end of the integral period, the integration error corresponding to the difference between the integrated voltage at the end of the integral period and the expected zero integral. Corresponding methods of gain tuning and a power converter are also described.