A display device includes first lead lines connecting the circuit signal lines with the driving integrated circuit, and second lead lines connecting the panel signal lines with the driving integrated circuit, wherein the second lead lines comprise a 2-1 sub-lead line configured to supply a scan-high voltage signal from the driving integrated circuit to the panel signal lines, and a 2-2 sub-lead line configured to supply a scan-low voltage signal from the driving integrated circuit to the panel signal lines, wherein the first lead lines comprises a 1-1 sub-lead line connected to the driving integrated circuit, a 1-1-1 sub-lead line separated from the 1-1 sub-lead line in a first direction, a 1-2 sub-lead line spaced apart from the 1-1 sub-lead line in a second direction intersecting the first direction, and a 1-2-1 sub-lead line spaced apart from the 1-2 sub-lead line in the second direction.

A circuit device 100 includes a light source driving value output unit 150 and a pixel value output unit 190. The light source driving value output unit 150 obtains a corrected intensity image Lled by correcting an intensity image Lint of an input image RGBin in a target display zone based on the light intensity distribution of a light source corresponding to the target display zone, and obtains a light source driving value Ldrv based on the largest corrected intensity value in the corrected intensity image Lled. The pixel value output unit 190 corrects pixel values of the input image RGBin based on the light source driving value Ldrv, and outputs the corrected pixel values as pixel values of an output image RGBout.

A backlight module and a driving method thereof are provided. The driving method includes following steps: first obtaining backlight data with N bits of data corresponding to each backlight unit in a current frame; then dividing time required by each backlight unit in the current frame to obtain N subfields with different durations; and finally outputting the N subfields of each backlight unit in a preset order, and controlling a scan line corresponding to the backlight unit to perform at least two scans in a first subfield, and a time interval between adjacent scans is less than a second threshold.

Embodiments of the present invention disclose an array substrate and a display panel. The array substrate includes a first substrate, and a first metal layer, a second metal layer, and a first shielding line sequentially disposed on the first substrate. The first metal layer includes a plurality of scan lines, the second metal layer includes a signal transmission line electrically connected to all of the scan lines, and at least a part of an orthographic projection of a wiring part of the signal transmission line on the first substrate coincides with an orthographic projection of the first shielding line on the first substrate.

A stereoscopic image display device includes a flat panel display unit, a lens array unit, and a light guide structure unit. The light guide structure unit includes a light guide microstructure. The light guide microstructure is disposed on a side of the lens array unit. A bottom angle of the light guide microstructure is defined as B, and a bottom length of the light guide microstructure is defined as P. The bottom angle B and the bottom length P of the light guide microstructure satisfies following conditions: (i) 15.5 degrees≤B≤83.5 degrees; and (ii) 10 micrometers≤P≤2,000 micrometers, such that an oblique viewing angle of the stereoscopic image display device falls within a range from 10 degrees to 60 degrees.

A device and method of an image processing system where a Field Sequential Color Delta Sigma Pulse Density Modulation is used for digital displays, where the digital displays are non-emissive. The device and method are a digital driving solution using Delta Sigma Encoding where N bit-per-component symbols at F1 frame-rate-per-second are represented using M bits-per-component symbols at F2 frame-rate-per-second, where N≥M and F2≥F1. The F2 frames are sent to a sequential color picker, which outputs frames with one color, followed by the next in a sequential pattern which reduces power consumption, increases color saturation, increases contrast, and increases brightness.

Disclosed are methods for compensating colors based on virtual chromaticity coordinate points and the related display devices. The present disclosure provides an electronic device. The electronic device comprises: a display comprising an array of pixels and a control circuit electrically connected to the display. Pixels in the array comprise a plurality of first sub-pixels defining a first color area on a chromaticity plane, a plurality of second sub-pixels defining a second color area on the chromaticity plane, and a plurality of third sub-pixels defining a third color area on the chromaticity plane. The control circuit is configured to receive an input image signal and generate a control signal to the display for driving each pixel of the display to output light in a virtual color gamut. The virtual color gamut of the display is among the first, second and third color areas on the chromaticity plane and does not overlap any of the first, second or third color areas.

A display device includes a substrate which includes a main area, a first auxiliary area extending from a first side of the main area in a first direction, and a sub-area extending from a second side of the main area in a second direction intersecting the first direction. Scan lines are disposed in the main area and the first auxiliary area and extend in the first direction. Data lines are disposed in the main area and the first auxiliary area and extend in the second direction. Sensor lines are disposed in the main area and the first auxiliary area and extend in the first direction. Sensor electrodes are disposed in the main area and the first auxiliary area and are connected to the sensor lines, respectively.

Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch. At least two of the latch output signals are activated at different time intervals.

The present application discloses a display apparatus and a drive method thereof. The display apparatus includes a display panel, and a panel chive circuit configured to drive the display panel; and a timing controller respectively transmits a signal to source drivers and a gate driver via the bus.