A pixel includes: a light emitting diode; a first transistor; a first capacitor connected between a first node and a gate electrode of the first transistor; a second transistor including a first electrode electrically connected to the gate electrode of the first transistor, a second electrode and a gate electrode which receives a first scan signal; and a third transistor including a first electrode electrically connected to the second electrode of the second transistor, a second electrode electrically connected to a third voltage line, and a gate electrode which receives a second scan signal. During an initialization period, an initialization voltage provided from the third voltage line is provided to the gate electrode of the first transistor through the third and second transistors, and, when the initialization period is terminated, at least one of the second transistor and the third transistor is turned off.

Disclosed are a gate driver and a display panel including the same. The gate driver according to an embodiment includes a plurality of signal transfer units cascade-connected via a carry line to which a carry signal is applied from a previous signal transfer unit, and an n.sup.th (n is a positive integer) signal transfer unit includes a first output unit configured to output a first gate signal to a first output node according to a voltage of a first control node configured to pull up an output voltage and a second control node configured to pull down the output voltage; and a second output unit configured to output a second gate signal in which a phase of the first gate signal is reversed to a second output node, wherein the second output unit may include a first pull-up transistor configured to output a high potential voltage to the second output node according to a voltage of a second control node of an (n-i).sup.th (i is a positive integer less than n) signal transfer unit; and a second pull-down transistor configured to output a first low potential voltage to the second output node according to a voltage of a first control node of an (n+j).sup.th (j is a natural number greater than n) signal transfer unit.

Disclosed are a pixel circuit and a display device including the same. The pixel circuit includes a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switch element including a first electrode connected to a fourth node, a gate electrode to which a scan pulse is applied, and a second electrode connected to the first node, and configured to be turned on according to a gate-on voltage of the scan pulse while a threshold voltage of the driving element is sensed; and a first capacitor connected between the second node and the fourth node.

A gate driver according to an embodiment and a display device using the same are discussed. The gate driver can output a gate signal to a pixel circuit having a driving element connected between a first power line and a first node, a light-emitting element connected between the first node and a second power line, and a switching element connected between the first node and a third power line and driven by the gate signal. The gate driver includes a first circuit unit to receive a carry signal from a previous signal transmission unit to charge or discharge a first control node and a second control node, and a second circuit unit having a first buffer transistor and a second buffer transistor configured to output the gate signal based on a first clock signal and a first low potential voltage according to potentials of the first and second control nodes.

A pixel circuit of a display device includes a driving element comprising a first electrode connected to a first node to which a pixel driving voltage is applied, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node, and configured to supply an electric current to a light-emitting element; a first switch element configured to be turned on according to a gate-on voltage and supply a data voltage to the second node; a first capacitor connected between the second node and the third node; a second capacitor connected between the third node and the fourth node; and a third capacitor connected between the fourth node and the first node, or between the fourth node and a power line to which the pixel driving voltage is applied.

A pixel circuit, a method for driving a pixel circuit and a display device. The pixel circuit includes a driving element including a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode to which a preset voltage is applied; a light emitting element including an anode electrode connected to a fourth node and a cathode electrode to which a low-potential power supply voltage is applied, the light emitting element being driven according to a current from the driving element; a first switch element connected between the first node and the second node; and a second switch element connected between the third node and the fourth node.

A display device, a gate drive circuit, a shift register and a control method are disclosed. The shift register includes a first shift register unit and a second shift register unit, the first shift register unit is configured to write a first control signal to the first node, and write a first clock signal to the first signal output terminal under control of a voltage of the first node; the second shift register unit is configured to write a second clock signal to the second signal output terminal under control of the voltage of the first node; during time of a frame, the first clock signal and a first input signal provided by a first signal input terminal are pulse signals, and the second clock signal is a DC signal.

Provided is a display device including a driving transistor, a switching unit, and a control unit. The driving transistor includes a control terminal, a first terminal, and a second terminal, and controls supply of current to a light emitting element, which is connected to the first terminal and emits light in accordance with the current amount, in accordance with a signal voltage applied to the control terminal. The switching unit can switch a conduction and non-conduction state, and, by being brought in the conduction state, forms a path that bypasses the light emitting element so that the current is not supplied to the light emitting element. The control unit performs control so that the switching unit is brought in the non-conduction state after the signal voltage is written into the control terminal, and controls a potential of the control terminal in synchronization with the control of the switching unit.

The present disclosure provides a display device including a display panel and a scan signal generator configured to generate a (1-1)th scan signal and a (1-2)th scan signal to be supplied to a first horizontal line of the display panel and a (2-1)th scan signal and a (2-2)th scan signal to be supplied to a second horizontal line of the display panel, wherein the scan signal generator includes a switch circuit, and an output circuit.

Disclosed is a display device, which includes a display panel including a plurality of pixels, and one of the plurality of pixels includes a light emitting device connected to a first reference node and that emits light, a driving transistor connected between a power supply line receiving a power supply voltage and the first reference node, a scan transistor connected between a data line receiving a data signal and the driving transistor and that receives a scan signal, a first capacitor connected between the first reference node and a second reference node, a shared transistor connected between the first reference node and the second reference node and that receives a shared control signal, and the first capacitor and the shared transistor are connected in series between the first reference node and the second reference node, and a control electrode of the driving transistor is connected to the second reference node.