A circuit device includes a scan line drive circuit that drives a plurality of scan lines of an electro-optical element, and an enable line drive circuit that outputs an enable signal to a plurality of pixel circuits. A field for constituting one image includes a plurality of subfields. The enable line drive circuit outputs an enable signal that is active in a partial period of a first display period corresponding to a first bit, which is a lower bit of display data. When the enable signal is active in a partial period of the first display period, a pixel is ON-state or OFF-state.

The electro-optical device includes a plurality of digital scanning lines, a plurality of analog scanning lines, a digital signal line, an analog signal line, and a plurality of pixel circuits. Each of the pixel circuits includes a light emitting element, a digital driving circuit, and an analog driving circuit. The digital driving circuit performs digital driving in which a drive current is supplied to the light emitting element in a period of a length corresponding to a grayscale value. The analog driving circuit performs analog current setting in which a current value of the drive current is set based on an analog data voltage. In a period in which the pixel circuit connected to an s-th digital scanning line and an s-th analog scanning line performs the analog current setting, the pixel circuit connected to a t-th digital scanning line and a t-th analog scanning line performs the digital driving.

The present embodiments disclose a pixel driving circuit and a display device including the same. A pixel driving circuit according to an embodiment of the present disclosure includes a first pixel circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of a plurality of subframes constituting a frame during a light-emitting period and a second pixel circuit storing a bit value of image data in a data writing period and generating the control signal based on the bit value and a clock signal in the light-emitting period.

A pixel circuit, a display substrate, a display device and a driving method are provided. The pixel circuit includes a data writing sub-circuit and a driving sub-circuit, and the data writing sub-circuit is connected to a scan signal terminal, a control signal terminal, a data signal terminal and a drive sub circuit. The data writing sub-circuit is used to output a data signal from the data signal terminal to the control node in response to a control signal provided by the control signal terminal and a scan signal provided by the scan signal terminal. The driving sub-circuit is connected to the control node, a power signal terminal and a light-emitting element, respectively, and is used to drive the light-emitting element to emit light in response to a potential of the control node and a power signal provided by the power signal terminal.

A backplane design for delivering image data in an efficient manner to a memory cell forming a part of a pixel driver comprises a word line design and a column data register release signal delivery design that are speed matched and a complementary bit line delivery design that is speed matched to a row decoder signal circuit operative to pull a word line driver to a state to enable the memory circuits of that row to receive data from the column drivers for each column. The speed matching is effective over a range of operating temperatures because the circuit designs are substantially identical.

A display substrate has a display area and a peripheral area around the display area. The display substrate includes a plurality of sub-pixels arranged in an array in the display area, and an interface circuit, at least two serial-to-parallel converters and at least one display driver that are in the peripheral area. The interface circuit is configured to receive target data including a plurality of serial display data. A serial-to-parallel converter in the at least two serial-to-parallel converters is used to convert the plurality of serial display data into parallel display data. The serial-to-parallel converter is electrically connected to one display driver to provide the parallel display data to the display driver. The display driver is used to output display driving signals to a plurality of sub-pixels according to the parallel display data.

A display control circuit applies to a LCoS panel including pixel units and a substrate. The display control circuit includes a pixel memory array circuit and a driving circuit. The pixel memory array circuit includes pixel memory units. A projection of the pixel memory array circuit on the substrate is in a projection of the pixel units on the substrate. The driving circuit includes a row driving circuit and a column driving circuit. A projection of the driving circuit on the substrate is outside the projection of the pixel units on the substrate. The driving circuit provides a modulation signal and pixel data. The pixel memory array circuit modulates the pixel data by the modulation signal to provide a pixel display voltage to each of the pixel units.

A micro-light emitting diode (micro-LED) display backplane includes a plurality of macro-pixels. Each macro-pixel includes: a contiguous two-dimensional (2-D) array of bitcells storing display data bits for driving a set of micro-LEDs of a 2-D array of micro-LEDs; and drive circuits configured to generate, based on the display data bits stored in the contiguous 2-D array of bitcells, pulse-width modulated (PWM) drive signals for driving the set of micro-LEDs of the 2-D array of micro-LEDs. In one example, the plurality of macro-pixels is grouped into a plurality of sub-arrays, where each sub-array of the plurality of sub-arrays includes a set of macro-pixels and a local periphery circuit next to the set of macro-pixels. The local periphery circuit includes, for example, a buffer, a repeater, a clock gating circuit for gating an input clock signal to the sub-array, and/or a sub-array decoder for selecting the sub-array.

An overcurrent protection circuit and display drive device, comprising: when input current of a front end corresponding to a logic signal experiences overcurrent, preventing the input current of the front end experiencing overcurrent from being transmitted to a drive chip, thereby preventing damage to the drive chip.

A display device includes a display substrate and a backplane substrate. The display substrate includes an array of micro-LEDs forming individual pixels. The backplane substrate includes a plurality of pixel logic hardware modules. Each pixel logic hardware module includes a local memory element configured to store a multi-bit pixel intensity value of a corresponding micro-LED for an image frame. The backplane substrate is bonded to a backside of the display substrate such that the pixel logic hardware modules are physically aligned behind the array of micro-LEDs and each pixel logic hardware module is electrically connected to a micro-LED of the corresponding pixel.