The present application provides a pixel driving circuit, which comprises a driving transistor, which comprises a gate terminal, a source terminal, and a drain terminal. The source terminal is respectively connected with a driving-voltage-signal terminal and a charge-voltage terminal via a first switch and a second switch. The charge-voltage terminal is connected with a data-voltage-signal terminal via a third switch. The gate terminal is connected with an initial-voltage-signal terminal via a fourth switch, and the gate terminal is connected with the drain terminal via a fifth switch. A first capacitor is connected with the gate terminal and the charge-voltage terminal, a second capacitor is connected with the gate terminal and a ground terminal. The present application further provides a pixel driving method and a display panel.

The invention provides a driver circuit structure for RGBW display panel, by arranging the driving TFTs on both sides of the data line to control the corresponding sub-pixels and disposing the plurality of scanning lines into two or four groups for interlaced scanning so that any data line only controlling sub-pixels of the same color during the time a group of scan lines being turned on. As such, the present invention can effectively improve the color shift when displaying solid color screen, improve the display quality, reduce the number of switches of data signal in the data line and reduce energy consumption.

An LED display module and a display apparatus are provided. The LED display module includes: an LED part including a plurality of first LEDs in a first row and a plurality of second LEDs in a second row; a first driver integrated circuit (IC) commonly connected to at least one of the plurality of first LEDs and at least one of the plurality of second LEDs, and a second driver IC commonly connected to another at least one of the plurality of first LEDs and another at least one of the plurality of second LEDs; a first switch connected to a plurality of the first LEDs disposed in odd-numbered columns of the first row, a second switch connected to a plurality of the second LEDs disposed in odd-numbered columns of the second row, a third switch connected to a plurality of the first LEDs disposed in even-numbered columns of the first row, and a fourth switch connected to a plurality of the second LEDs disposed in even-numbered columns of the second row; and a controller configured to control the first to fourth switches to be sequentially turned on.

A display apparatus includes a display panel and a first gate driver. The display panel includes a plurality of data lines extending in a first direction, and a plurality of gate lines extending in a second direction obliquely inclined toward the first direction and spaced apart from each other in a third direction crossing the second direction. The plurality of gate lines includes a first gate line group and a second gate line group respectively disposed in first and second display areas of the display panel. The first gate driver is configured to drive at least one gate line of the second gate line group while driving at least one gate line of the first gate line group.

The embodiment of the present disclosure discloses an array substrate. The array substrate comprises: a base, a plurality of first scanning lines, a plurality of second scanning lines, a plurality of data lines, a common electrode line, and a plurality of pixel units. Each of the pixel units comprises: a first electrode, a second electrode, a switch transistor, a shared transistor and a shared capacitor. The switch transistor has a first terminal coupled to the second electrode, a second terminal coupled to one of the plurality of data lines, a bottom gate coupled to one of the plurality of first scanning lines, and a top gate coupled to one of the plurality of second scanning lines, and is configured to transfer a data signal of the data line to the second electrode under the control of a first scanning signal and a second scanning signal.

A liquid crystal display (LCD) apparatus includes a color filter layer, a liquid crystal (LC) layer, and a pixel circuit layer. The color filter layer includes a plurality of color filters corresponding to an array of pixels arranged in M rows and N columns. The number of the color filters is k times of the number of the pixels. The LC layer is divided into a plurality of LC regions, each of which corresponds to a respective one of the color filters. The pixel circuit layer includes a plurality pixel circuits, each of which is configured to drive a respective one of the LC regions. The pixel circuit layer also includes xM gate lines and (k/x)N source lines, where x is a fraction larger than one, and each of xM and (k/x)N is a positive integer.

An apparatus includes an active region, a source driving circuit, and a light emitting driving circuit. The active region includes an array of light emitting elements corresponding to an array of pixels arranged in M rows and N columns. The number of the array of light emitting elements is k times of the number of the array of pixels. The apparatus includes xM light emitting lines and (k/x)N source lines, wherein x is a positive fraction, and each of xM and (k/x)N is a positive integer. The source driving circuit is operatively coupled to the active region via the (k/x)N source lines and configured to write display data of a frame to the array of light emitting elements. The light emitting driving circuit is operatively coupled to the active region via the xM light emitting lines and configured to cause the array of light emitting elements to emit light.

In a liquid crystal display device (100), each pixel row group is selected by a common scan signal voltage, each pixel row group including N pixel rows which adjoin one another in a column direction. Where two pixel rows which adjoin each other in a column direction and which are included in different pixel row groups are a first pixel row and a second pixel row, the first pixel row includes a pixel which has a pixel electrode (16) capacitively coupled with a gate bus line (12) which is associated with the second pixel row. When the first pixel row is included in the q.sup.th group, the second pixel row is included in the (q+1).sup.th group. A scan signal voltage supplied to gate bus lines which are associated with the (q+1).sup.th group switches from low to high before a scan signal voltage supplied to gate bus lines which are associated with the q.sup.th group switches from high to low.

A gate driver can include a plurality of stages configured to output scan signals. An output of each stage among the plurality of stages is configured to connect to a pair of gate lines that are adjacent to each other, output an odd-numbered scan signal to an odd-numbered line among the pair of gate lines according to a first driving frequency, and output an even-numbered scan signal to an even-numbered line among the pair of gate lines according to the first driving frequency. Also, a phase difference between the odd-numbered scan signal and the even-numbered scan signal is 180 degrees.

An apparatus includes an active region, gate lines, source lines, a gate driver, and a source driver. The active region includes a plurality of subpixels. The subpixels correspond to an array of pixels arranged in M rows and N columns. The number of the subpixels is k times of the number of the pixels. The apparatus includes xM gate lines and (k/x)N source lines, where x is a fraction between 1 and 2, and each of xM and (k/x)N is a positive integer. The gate driver is operatively coupled to the active region via the xM gate lines and configured to scan the plurality of subpixels. The source driver is operatively coupled to the active region via the (k/x)N source lines and configured to write display data in a frame to the plurality of subpixels.