A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

A system includes, according to one embodiment, a magnetic head having a plurality of write transducers configured to store data to tracks of a sequential access medium and a plurality of read transducers. Each read transducer is configured to read data from the sequential access medium after being written thereto by a corresponding write transducer. A first of the read transducers is aligned with a first of the write transducers, wherein the output of the first read transducer is produced during read-while-write. The system also includes a controller and logic integrated with and/or executable by the controller. The logic is configured to read, using the plurality of read transducers, encoded data from a plurality of tracks of the sequential access medium simultaneously. The logic is configured to determine that one or more tracks of the sequential access medium are dead within a sliding window and rewrite a set of encoded data from the one or more dead tracks to one or more live tracks in a rewrite area of the sequential access medium. Other systems, methods, and computer program products are described according to more embodiments.

In one embodiment, a system includes a magnetic head having a plurality of write transducers and a plurality of read transducers. Each read transducer is configured to read data from a sequential access medium after being written thereto by a corresponding write transducer. The system also includes a controller and logic integrated with and/or executable by the controller. The logic is configured to read, using the plurality of read transducers, encoded data from a plurality of tracks of the sequential access medium simultaneously. The logic is also configured to determine that one or more tracks of the sequential access medium are dead within a sliding window. Moreover, the logic is configured to rewrite a set of encoded data from the one or more dead tracks to live tracks in a rewrite area of the sequential access medium. Other systems, methods, and computer program products are described according to more embodiments.

In one embodiment, a system includes a magnetic head having a plurality of write transducers and a plurality of read transducers. Each read transducer is configured to read data from a sequential access medium after being written thereto by a corresponding write transducer. The system also includes a controller and logic integrated with and/or executable by the controller. The logic is configured to read, using the plurality of read transducers, encoded data from a plurality of tracks of the sequential access medium simultaneously. The logic is also configured to determine that one or more tracks of the sequential access medium are dead within a sliding window. Moreover, the logic is configured to rewrite a set of encoded data from the one or more dead tracks to live tracks in a rewrite area of the sequential access medium. Other systems, methods, and computer program products are described according to more embodiments.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.

A method for decoding a headerized sub data set (SDS) according to one embodiment includes decoding a header from a headerized SDS to obtain a SDS. C1 and C2 decoding are performed on the SDS in a number of iterations based on a number of interleaves in each row of the SDS. A number of columns of the SDS are overwritten with successfully decoded C2 codewords. A number of rows of the SDS are overwritten with successfully decoded C1 codewords. A number of C1 and/or C2 codewords of the SDS are erased. Remaining rows and/or columns of the SDS are maintained as uncorrected. The SDS is output when all rows of the SDS include only C1 codewords and all columns of the SDS include only C2 codewords.