A memory system includes a memory device, a command clock (CK_t clock) that provides a first clock signal at a first frequency, and a data path clock (WCK_t clock) that provides a second clock signal at a second frequency different than the first frequency. Data path circuitry is synchronized with the WCK_t clock and provides an error detection code (EDC) hold pattern during an idle state. EDC hold pattern synchronization logic synchronizes a start of transmission of the EDC hold pattern synchronous to the CK_t clock.

According to one embodiment, a magnetic disk device includes a read control system that extracts scrambled data from media data read from a medium and inspection data associated with a seed value at the time of write, generates inspection data for data extracted from the media data, obtains from the inspection data and inspection data extracted from the media data, a seed value associated with both, compares this seed value with the seed value expected by the controller, and evaluates, when the comparison result is a mismatch, the data as an error, whereas when match, descrambles the data extracted from the media data using the seed value.

According to the embodiment, an HDC receives a plurality of data segments from a host, and executes generation and addition of a first code and output of a data segment to which the first code is added to each data segment. An HDC calculates exclusive OR with respect to the first codes, and outputs obtained first information. The RWC performs data conversion and calculation of exclusive OR on the plurality of data segments to which the first code is added, and outputs the plurality of data segments after the data conversion and a track parity obtained by the calculation of the exclusive OR. The RWC acquires the first code from the plurality of data segments. The RWC calculates exclusive OR with respect to a group of the second codes which are the acquired first codes to acquire second information. The RWC compares the first information with the second information.

An electronic device includes a memory having memory locations being subject to transient faults and permanent faults, and a fault detection circuit coupled to the memory. The fault detection circuit is configured to read the memory locations at a first time, and determine a first fault count and fault map signature including the transient and permanent faults at the first time based upon reading the plurality of memory locations, and to store the first fault count and fault map signature. The fault detection circuit is configured to read the memory locations at a second time and determine a second fault count and fault map signature including the transient and permanent faults at the second time based upon reading the memory locations, and compare the stored first fault count and fault map signature with the second fault count and fault map signature to determine a permanent fault count.

The present disclosure relates to a safety system having a memory unit configured to store a series of executable instructions. In some embodiments, the executable instructions are grouped into code parts, and each code part is assigned a predefined code value. A processor is configured to execute the series of executable instructions, and to output the predefined code values respectively as the code parts are executed. A program flow monitoring (PFM) unit is configured to respectively receive the predefined code values from the processor, such that the PFM unit generates an error-checking value from the predefined code values. A verification unit is configured to compare the error-checking value to an expected return value to determine whether the series of executable instructions executed properly.

Systems, methods, and computer program products to perform an operation comprising receiving a first unit of video data on a first input/output (I/O) channel, of a plurality of I/O channels of a digital video recorder, computing a first value by applying an error-detecting function to the first unit of video data, attempting to write the first unit of video data to a storage location of a storage device communicably coupled to the digital video recorder, computing, after attempting to write the first unit of video data, a second value by applying the error-detecting function to a data stored at the storage location of the storage device, and upon determining that the first and second values are not equal, storing an indication that the first unit of video data was not successfully written to the storage location of the storage device.

According to the embodiment, an HDC receives a plurality of data segments from a host, and executes generation and addition of a first code and output of a data segment to which the first code is added to each data segment. An HDC calculates exclusive OR with respect to the first codes, and outputs obtained first information. The RWC performs data conversion and calculation of exclusive OR on the plurality of data segments to which the first code is added, and outputs the plurality of data segments after the data conversion and a track parity obtained by the calculation of the exclusive OR. The RWC acquires the first code from the plurality of data segments. The RWC calculates exclusive OR with respect to a group of the second codes which are the acquired first codes to acquire second information. The RWC compares the first information with the second information.

According to one embodiment, a magnetic disk device includes a read control system that extracts scrambled data from media data read from a medium and inspection data associated with a seed value at the time of write, generates inspection data for data extracted from the media data, obtains from the inspection data and inspection data extracted from the media data, a seed value associated with both, compares this seed value with the seed value expected by the controller, and evaluates, when the comparison result is a mismatch, the data as an error, whereas when match, descrambles the data extracted from the media data using the seed value.

An electronic device includes a memory having memory locations being subject to transient faults and permanent faults, and a fault detection circuit coupled to the memory. The fault detection circuit is configured to read the memory locations at a first time, and determine a first fault count and fault map signature including the transient and permanent faults at the first time based upon reading the plurality of memory locations, and to store the first fault count and fault map signature. The fault detection circuit is configured to read the memory locations at a second time and determine a second fault count and fault map signature including the transient and permanent faults at the second time based upon reading the memory locations, and compare the stored first fault count and fault map signature with the second fault count and fault map signature to determine a permanent fault count.

In one embodiment, a system for cycle-slip resilient iterative read channel operation includes a processor and logic integrated with and/or executable by the processor. The logic is configured to, in an iterative process until a maximum number of iterations has been reached or a valid codeword is produced, execute cycle-slip detection on signal samples to detect one or more cycle-slip events. Also, the logic is configured to selectively alter a timing estimate driving a phase-locked loop (PLL) during any time interval determined to experience a cycle slip in a first pass as indicated by one or more cycle-slip pointers. Additionally, the logic is configured to generate a set of decisions provided by a detector and generate a set of decisions provided by a decoder. Moreover, the logic is configured to output decoding information relating to the signal samples in response to a decoding algorithm producing a valid codeword.