A semiconductor memory device is provided. The semiconductor memory device includes a maintaining circuit, a sensing circuit, an output circuit, and a verification circuit. The maintaining circuit is configured to maintain data read from a memory cell array and output the data to a data bus in response to a column selection signal. The sensing circuit is configured to sense the data on the data bus in response to at least one sensing enable signal. The output circuit is configured to output the data sensed by the sensing circuit. The verification circuit is configured to verify an operation margin of the sensing circuit and output a verification result. The timing of the at least one sensing enable signal is set according to the verification result of the verification circuit.

A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

A semiconductor memory device is provided. The semiconductor memory device includes a column selection circuit, a sensing circuit, an output circuit, and a verification circuit. The column selection circuit selects n-bit data from data read from a memory cell array according to a column selection signal and outputs the selected n-bit data to an n-bit data bus. The sensing circuit senses the n-bit data on the data bus in response to an activation signal. The output circuit selects m-bit data from the n-bit data sensed by the sensing circuit in response to an internal clock signal synchronized with a serial clock signal applied from outside and outputs the selected m-bit data from output terminals. The verification circuit compares the data sensed by the sensing circuit with the data output by the output circuit to verifying the correctness of read-out data.

Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.

A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

A memory device includes a serial interface controller that receives and operates using a serial message having a format that includes a command field of the serial message. The format also includes a register address field of the serial message immediately following the command field. The format further includes a data field of the serial message immediately following the register address field.

An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

A byte-programming method for programming data from a page register to a non-volatile memory array includes reading data of a selected byte in the page register and programming the data to the memory cells of the non-volatile memory corresponding to a selected column address; determining whether to update an array column address according to the selected column address, which includes: determining whether the data of the selected byte meets specified content; when the data of the selected byte meets the specified content, not updating the array column address; and when the data of the selected byte doesn't meet the specified content, updating the array column address according to the selected column address; and determining whether the selected column address is the last column address.