In an exemplary embodiment, the disclosure provides a memory circuit which includes a dual port memory cell for storing a binary value accessed through a first port and a second port, a first WL switch connected to the dual port memory cell and controlled by a first WL voltage, a second WL switch connected to the dual port memory cell and controlled by a second WL voltage, a BL connected to the first WL switch for accessing the memory cell through the first port and having a first BL voltage, a second BL connected to the second WL switch for accessing the memory cell through the second port and having a second BL voltage, a BL selection circuit connected to the second WL switch for selecting the second BL, and a BL voltage pull down circuit connected to the BL selection circuit and the second WL switch.

Memory devices with half-width data path or data buses clocked by double-pumped strobe signals are disclosed herein. The methods and devices may employ a single delay chain (e.g., a column access strobe (CAS) chain) to perform the double-pumped operations. The delay chain may include multiple delay elements that may generate one or two pulses based on the double-pumped strobe signals. Methods for interfacing, such as read and write methods are also disclosed.

A computer device, a setting method for a memory module, and a mainboard are provided. The computer device includes a memory module, a processor, and the mainboard. A basic input output system (BIOS) of the mainboard stores an extreme memory profile (XMP). When the processor performs the BIOS so that the computer device displays a user interface (UI), the BIOS displays an overclocking option corresponding to the XMP in a selection list of the UI. When the BIOS receives a selection request corresponding to the overclocking option of the selection list, the BIOS reads multiple memory setting parameters corresponding to the XMP, and configures the memory module according to the memory setting parameters.

A marching memory includes an alternating periodic array of odd-numbered columns (U.sub.1, U.sub.2, . . . , U.sub.n1, U.sub.n) and even-numbered columns (Ur.sub.1, Ur.sub.2, . . . , Ur.sub.n1, Ur.sub.n). Each of the odd-numbered columns (U.sub.1, U.sub.2, . . . , U.sub.n1, U.sub.n) has a sequence of front-stage cells aligned along a column direction so as to store a set of moving information of byte size or word size. And each of the even-numbered columns (Ur.sub.1, Ur.sub.2, . . . , Ur.sub.n1, Ur.sub.n) has a sequence of rear-stage cells aligned along a column direction so as to store the set of moving information, so that the set of moving information can be transferred synchronously, step by step, along a direction orthogonal to the column direction.

Memory devices with half-width data path or data buses clocked by double-pumped strobe signals are disclosed herein. The methods and devices may employ a single delay chain (e.g., a column access strobe (CAS) chain) to perform the double-pumped operations. The delay chain may include multiple delay elements that may generate one or two pulses based on the double-pumped strobe signals. Methods for interfacing, such as read and write methods are also disclosed.

Memory devices with half-width data path or data buses clocked by double-pumped strobe signals are disclosed herein. The methods and devices may employ a single delay chain (e.g., a column access strobe (CAS) chain) to perform the double-pumped operations. The delay chain may include multiple delay elements that may generate one or two pulses based on the double-pumped strobe signals. Methods for interfacing, such as read and write methods are also disclosed.

A semiconductor memory device includes bank arrays, row decoders, column decoders, a timing control circuit and repeaters. The bank arrays are distributed in a core region of a substrate, and each bank array includes sub-array blocks and includes a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines. Each row decoder is disposed adjacent each bank array in a first direction. Each column decoder is disposed adjacent each bank array in a second direction. The timing control circuit, which is disposed in a peripheral region of the substrate, generates a first control signal to control the word-lines and a second control signal to control the bit-lines in response to operation control signals. Each repeater is disposed adjacent each column decoder and each repeater transfers the first and second control signals to the sub-array blocks in the second direction.

An SRAM controller for performing sequential accesses using internal ports that operate concurrently on different rows. Each internal port includes a row address strobe (RAS) timer that generates clock signals controlling the timing of operations during a RAS phase in which word line decoding is performed once for a group of bit cells being accessed. The RAS phase can involve additional conditioning operations, such as precharging of local bits lines associated with the group of bit cells. The RAS phase is followed by an input/output (IO) phase in which individual bit cells are accessed in sequential address order using a column select signal generated by an IO timer. The RAS phase of a first internal port can be at least partially overlapped by the IO phase of a second internal port to hide the RAS latency of the first internal port. The IO timer can be shared among internal ports.

A memory control device, which includes a signal generating circuit, a data writing circuit and a repeating circuit. The repeating circuit is coupled to the data writing circuit. The signal generating circuit is configured to generate a data strobe signal and send the data strobe signal to a memory. The data strobe signal comprises a preamble signal. The data writing circuit is configured to write a series of data to the memory according to the data strobe signal. The repeating circuit is configured to repeat a first data of the series of data in a period of the preamble signal.

A memory control device, which includes a signal generating circuit, a data writing circuit and a repeating circuit. The repeating circuit is coupled to the data writing circuit. The signal generating circuit is configured to generate a data strobe signal and send the data strobe signal to a memory. The data strobe signal comprises a preamble signal. The data writing circuit is configured to write a series of data to the memory according to the data strobe signal. The repeating circuit is configured to repeat a first data of the series of data in a period of the preamble signal.