Embodiments of the present invention provide a storage cell and a data read/write method and storage array thereof. The storage cell includes a bit line, a tunnel junction, and four access transistors. Each access transistor includes at least an active region. The active region includes a source. The sources of the access transistors are all electrically connected to a first end of the tunnel junction. A second end of the tunnel junction is electrically connected to the bit line, and the bit line extends along a first direction. The active regions of the access transistors are isolated from one another. Long-side extension directions of the active regions of the access transistors are the same, and a first angle θ is formed between the long-side extension directions of the active regions and the first direction; wherein θ is a non-right angle.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

Memory devices have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells are located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices also include compensation circuitry configured to determine which driving access lines driving a target memory cell of the plurality of memory cells has the most distance between the target memory cell and a respective driver. The plurality of access lines comprise the driving access lines. The compensation circuitry also is configured to output compensation values to adjust the voltages of the driving access lines based on a polarity of the voltage of the longer driving access line.

Example magnetic random access memories are described. One example magnetic random access memory includes a plurality of structural units and a plurality of voltage control lines. The plurality of voltage control lines are in parallel with each other. Planes in which the plurality of structural units are located are in parallel with each other, and a plane in which each of the plurality of structural units is located is perpendicular to the plurality of voltage control lines. Each structural unit includes a multi-layer storage structure including multiple layers that are stacked in sequence. Each layer of the multi-layer storage structure includes an electrode line and a plurality of storage units disposed on the electrode line. Each of the plurality of storage units includes a magnetic tunnel junction. A first end of each storage unit is connected to the electrode line, and a second end of each storage unit is connected to one of the plurality of voltage control lines.

Provided are a magnetoresistive element, a magnetic memory device, and a writing and reading method for a magnetic memory device, in which an aspect ratio of a junction portion can be decreased. A magnetoresistive element 1 of the invention, includes: a heavy metal layer 2 that is an epitaxial layer; and a junction portion 3 including a recording layer 31 that is provided on the heavy metal layer 2 and includes a ferromagnetic layer of an epitaxial layer magnetized in an in-plane direction, which is an epitaxial layer, a barrier layer 32 that is provided on the recording layer 31 and includes an insulating body, and a reference layer 33 that is provided on the barrier layer 32 and has magnetization fixed in the in-plane direction, in which the recording layer 31 is subjected to magnetization reversal by applying a write current to the heavy metal layer 2.

A memory device which includes a control logic circuit that generates a write enable signal based on a write command, a first memory cell connected with a first word line and a first column line, a first write circuit that receives first write data to be stored in the first memory cell through a first write input/output line and applies a write voltage to a first data line based on the first write data in response to the write enable signal, and a first column multiplexer circuit that selects the first column line and connects the first column line with the first data line in response to a first column select signal, such that the write voltage is applied to the first memory cell. The first write circuit applies the write voltage to a bulk port of the first column multiplexer circuit in response to the write enable signal.

According to one embodiment, an arithmetic device includes a first computational circuit including a first string, the first string having a first magnetoresistive effect element on a first conducting layer; a second computational circuit including a second strings, the second string having second magnetoresistive effect element on a second conducting layer; a third computational circuit executing computational processing using a first signal from the first computational circuit and a second signal from the second computational circuit; and a control circuit. The control circuit sets a condition on write operations with respect to at least one of the first and second magnetoresistive effect elements, based on information related to write error in at least one of the first and second magnetoresistive effect elements.

A magnetic memory device includes a three-terminal type memory cell. A first terminal is connected to a first conductor layer. A second terminal is connected to a second conductor layer. A third terminal is connected to a third conductor layer. The memory cell includes a fourth conductor connected to the first conductor layer, the second conductor layer, and the third conductor layer. A magnetoresistance effect element of the memory cell is coupled between the third conductor layer and the fourth conductor layer. A first switching element is coupled to the second conductor layer and the fourth conductor layer. A second switching element coupled to the first conductor layer and the third conductor layer. The fourth conductor layer includes a first ferromagnetic layer and a first non-magnetic layer. The first non-magnetic layer comprises at least one of ruthenium, iridium, rhodium, or osmium.

A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element, a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on the cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.