Memory cells and methods of forming thereof are disclosed. The memory cell includes a substrate and first and second select transistors. The first select transistor serves as a write selector and the second select transistor serves as a read selector. The gate of first select transistor is coupled to a write wordline (WL_w) and the gate of the second select transistor is coupled to a read/write wordline (WL_r/w). The source regions of the first and second select transistors are coupled to a source line (SL). A body well is disposed in the substrate. The body well serves as a body of the first and second select transistors. A back bias is applied to the body of the select transistors. A storage element which includes a magnetic tunnel junction (MTJ) element is coupled with a bitline (BL) and the first and the second select transistors.

A method for operating a memory system includes receiving thermal data indicating a temperature at addresses in a memory array, and a write request associate with data. An address of the write request is decoded. It is determined whether a temperature at the address of the write request is above a threshold temperature. The data is sent to a short latency write queue responsive to determining that the temperature is not above the threshold temperature.

Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ) or other suitable resistive memory element to produce stochastic switching. In embodiments, the switch device may produce a switching output according to a stochastic switching probability of the switch device. In embodiments, a bit line or a source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output which enables a determination of whether the respective weight value is to be updated. Other embodiments may also be described and claimed.

According to one embodiment, a semiconductor memory device includes a first memory cell array including a first memory cell having a variable resistive element, a second memory cell array including a second memory cell having the variable resistive element, a reference signal generation circuit which generates a reference signal, a sense amplifier having a first input terminal and a second input terminal, and a read enable control circuit which generates a read enable signal in accordance with a command from outside and control switching between a single cell read mode and a twin cell read mode.

A semiconductor device includes a bit-line sense amplifier (S/A) circuit configured to sense and amplify data stored in a resistive memory cell according to a reference current. The bit-line S/A circuit includes a cross-coupled latch circuit and a write latch circuit. The cross-coupled latch circuit is coupled to an input/output circuit via a first line and a complementary first line. The cross-coupled latch circuit is configured to receive write data via the first line, and to latch the write data during a data write operation. The write latch circuit is coupled to the cross-coupled latch circuit, and configured to store the write data in the resistive memory cell via a second line during the data write operation.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive word line layers located over a substrate, and a plurality of vertical memory strings. Each vertical memory string includes a series connection of a memory stack structure and a selector element. Each of the memory stack structures extends through the alternating stack and includes a respective memory film and a respective vertical semiconductor channel. Each of the selector elements includes a two terminal device that is configured to provide at least two different resistivity states.

A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows in each of the banks; and an address latch circuit configured to latch a full address specifying one of the word lines, the full address including a first address and a second address. The address latch circuit receives a first command and a second command to latch the first address and the second address in accordance with the first command and the second command, respectively. Paths for the first address and the second address are configured to be separate from each other.

A multi-state MRAM device comprises N overlapping ovals defining a free ferromagnetic region. The size of the free ferromagnetic region is controlled the shape anisotropy of the configuration via at least a aspect ratio greater than 2, of the free ferromagnetic region. The free ferromagnetic region has a magnetic moment spontaneously aligned along the long axis in each oval outside the center region. A center magnetic moment has a multitude of exactly 2*N stable orientations determined by the magnetic moments in the segments of the ovals outside the center region. An embodiment is an MRAM device using tunneling junctions to achieve a multi-state memory configuration. Certain embodiments includes an electrically conducting heavy-metal layer disposed adjacent to and connected with the free ferromagnetic region. Some embodiments include a topological insulating material, such as Bi.sub.2Se.sub.3. Magnetic moment reversal in the ovals may be determined by spin-transfer torque associated with the electrically conducting layer.

A semiconductor memory device includes a memory cell array comprising a plurality of spin torque transfer-magnetic random access memory (STT-MRAM) cells connected to a plurality of word lines, a plurality of bit lines and a plurality of sense lines. A peripheral circuitry supplies cell current to the memory cells during read/write operations, such that the cell current supplied to memory cells of a selected word line vary according to a position of a word line group including the selected word line.

A gesture manipulation method and a gaming system are disclosed herein. The gesture manipulation method is suitable for an electronic apparatus including a touch sensor and means for displaying. The gesture manipulation method includes following steps. A gesture input is detected by the touch sensor when a visual card image is displayed on the means for displaying and the visual card image shows a back side of at least a playing card. When at least one contact point of the gesture input is detected to move along a specific pattern relative to the visual card image, a corresponding function is triggered or the visual card image is adjusted in response to the gesture input moved along the specific pattern.