A variable resistance memory device includes: a memory cell including a first and second sub memory cell; and a first, second and third conductor. The first sub memory cell is above the first conductor, and includes a first variable resistance element and a first bidirectional switching element. The second sub memory cell is above the second conductor, and includes a second variable resistance element and a second bidirectional switching element. The second conductor is above the first sub memory cell. The third conductor is above the second sub memory cell. The variable resistance memory device is configured to receive first data and to write the first data to the memory cell when the first data does not match second data read from the memory cell.

According to one embodiment, a memory device includes first and second wiring lines, memory cells between first and second wiring lines, first and second common wiring lines, a first selecting circuit between one ends of the first wiring lines and the first common wiring line, and a second selecting circuit between the other ends of the first wiring lines and the first common wiring line. A path between the first wiring line and the first common wiring line through the first selecting circuit and a path between the first wiring line and the first common wiring line through the second selecting circuit are defined as first and second paths, one of the first and second paths is set to an electrically conductive state.

An embedded eMRAM device for eFlash replacement including an MTJ pillar located between a top electrode and a bottom electrode for forming an MRAM array. The bottom electrode is disposed above a substrate and surrounded by a first dielectric spacer, while the top electrode is disposed above the MTJ pillar and surrounded by a second dielectric spacer. A bottom metal plate is disposed on opposing sides of the bottom electrode between first and second dielectric layers and is electrically separated from the bottom electrode by the first dielectric spacer. A top metal plate is disposed on opposing sides of the top electrode between third and fourth dielectric layers and is electrically separated from the top electrode by the second dielectric spacer. A bias voltage applied to the top metal plate and the bottom metal plate generates an external electric field on the MTJ pillar for creating a VCMA effect.

A circuit includes an array of OTP cells, an array of NVM cells, an amplifier coupled to each of the array of OTP cells and the array of NVM cells, and a control circuit configured to generate one or more control signals. Responsive to the one or more control signals, the amplifier is configured to generate an output voltage based on a current received from the array of OTP cells in a first configuration, and generate the output voltage based on a voltage received from the array of NVM cells in a second configuration.

A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element, and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.

Some embodiments relate to a probabilistic random number generator. The probabilistic random number generator includes a memory cell comprising a magnetic tunnel junction (MTJ), and an access transistor coupled to the MTJ of the memory cell. A variable current source is coupled to the access transistor and is configured to provide a plurality of predetermined current pulse shapes, respectively, to the MTJ to generate a bit stream that includes a plurality of probabilistic random bits, respectively, from the MTJ. The predetermined current pulse shapes have different current amplitudes and/or pulse widths corresponding to different switching probabilities for the MTJ.

The present disclosure provides a storage unit, a data writing method and a data reading method thereof, a memory and an electronic device. The storage unit includes a semiconductor substrate, a first insulating medium layer, a ferroelectric thin film layer, a bottom electrode, a tunnel junction, a first metal interconnection portion, a second metal interconnection portion, a third metal interconnection portion and a fourth metal interconnection portion. The first insulating medium layer is formed on the semiconductor substrate, the ferroelectric thin film layer is disposed on the first insulating medium layer, the bottom electrode is formed on the ferroelectric thin film layer, and the tunnel junction is formed on the bottom electrode. The first metal interconnection portion is connected to a first end of the bottom electrode, and the third metal interconnection portion is connected to a second end of the bottom electrode. The second metal interconnection portion is connected to the ferroelectric thin film layer, and the fourth metal interconnection portion is connected to the tunnel junction. As compared with the prior art, the present disclosure can control a directional flipping of the magnetic moment in the tunnel junction based on the ferroelectric thin film layer provided. Based on the structural design of the storage unit, the present disclosure does not require an external magnetic field, and fully meets the requirement of high integration of the device.

Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.

A cross-point SOT-MRAM cell includes: a first SHE write line; a second SHE write line non-colinear to the first SHE write line; a cross-point free layer comprising a first free layer, a second free layer, and a dielectric layer disposed between the first and the second free layers, the cross-point free layer configured to store a magnetic bit and located between and in contact with both the first SHE write line and the second SHE write line; and a remote sensing MTJ located in a vicinity of the cross-point free layer, wherein a free layer sensor of the remote sensing MTJ is in contact with one of the first SHE write line and the second SHE write line.

Provided are a magnetoresistive element, a magnetic memory device, and a writing and reading method for a magnetic memory device, in which an aspect ratio of a junction portion can be decreased. A magnetoresistive element 1 of the invention, includes: a heavy metal layer 2 that is an epitaxial layer; and a junction portion 3 including a recording layer 31 that is provided on the heavy metal layer 2 and includes a ferromagnetic layer of an epitaxial layer magnetized in an in-plane direction, which is an epitaxial layer, a barrier layer 32 that is provided on the recording layer 31 and includes an insulating body, and a reference layer 33 that is provided on the barrier layer 32 and has magnetization fixed in the in-plane direction, in which the recording layer 31 is subjected to magnetization reversal by applying a write current to the heavy metal layer 2.