A lookup table circuit constituting a programmable logic device includes: a memory cell array including a plurality of memory cells, each having a resistive memory element; a selection circuit connected to the memory cell array and configured to output, to the memory cell array, a single cell-select signal or two or more cell-select signals for selecting a single memory cell or two or more memory cells among the plurality of memory cells, based on input of a plurality of logic signals; and a read circuit connected to the memory cell array and configured to read data from the single memory cell or the two or more memory cells selected by the single cell-select signal or the two or more cell-select signals, among the plurality of memory cells. The selection circuit is separated from a path along which the read circuit is configured to read data from the memory cell array.

A memory unit, array and operation method thereof are provided. The memory unit includes at least one P-type driver having a first end coupled to a power source, a second end and a control end coupled to a word line; a memory cell having a first end coupled to the second end of the P-type driver, and a second end coupled to a bit line.

The present invention is directed to a nonvolatile memory device including a plurality of memory cells arranged in rows and columns, a plurality of word lines with each connected to a respective row of the memory cells along a row direction, a plurality of bit lines with each connected to a respective column of the memory cells along a column direction; a column decoder connected to the bit lines; a plurality of sense amplifiers connected to the column decoder; and a plurality of sense amplifier control circuits. Each of the sense amplifiers is connected to a unique one of the sense amplifier control circuits. Each of the sense amplifier control circuits includes a current detector circuit for detecting a sensing current, a current booster circuit for boosting the sensing current, and a timer circuit for providing a delayed trigger for a respective one of the sense amplifiers connected thereto.

A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.

According to one embodiment, an arithmetic device includes a first computational circuit including a first string, the first string having a first magnetoresistive effect element on a first conducting layer; a second computational circuit including a second strings, the second string having second magnetoresistive effect element on a second conducting layer; a third computational circuit executing computational processing using a first signal from the first computational circuit and a second signal from the second computational circuit; and a control circuit. The control circuit sets a condition on write operations with respect to at least one of the first and second magnetoresistive effect elements, based on information related to write error in at least one of the first and second magnetoresistive effect elements.

According to one embodiment, a magnetic memory device includes a memory cell including a magnetoresistance effect element, a switching element, and a resistance element connected in series. The resistance element has an asymmetric current-voltage characteristic, and when data is read from the memory cell, a first voltage in a reverse direction is applied to the resistance element, and a resistance value of the resistance element at a time when the first voltage is applied is greater than a resistance value of the resistance element at a time when a second voltage in a forward direction having an absolute value identical to an absolute value of the first voltage is applied.

A magnetic memory device includes a three-terminal type memory cell. A first terminal is connected to a first conductor layer. A second terminal is connected to a second conductor layer. A third terminal is connected to a third conductor layer. The memory cell includes a fourth conductor connected to the first conductor layer, the second conductor layer, and the third conductor layer. A magnetoresistance effect element of the memory cell is coupled between the third conductor layer and the fourth conductor layer. A first switching element is coupled to the second conductor layer and the fourth conductor layer. A second switching element coupled to the first conductor layer and the third conductor layer. The fourth conductor layer includes a first ferromagnetic layer and a first non-magnetic layer. The first non-magnetic layer comprises at least one of ruthenium, iridium, rhodium, or osmium.

A semiconductor memory device has a first wiring extending in a first direction and a second wiring extending in a second direction. The first and second wirings are spaced from each other in a third direction. The second wiring has a first recess facing the first wiring. A resistance change memory element is connected between the first and second wirings. A conductive layer is between the resistance change memory element and the second wiring and includes a first protrusion facing the second wiring. A switching portion is between the conductive layer and the second wiring and includes a second recess facing the conductive layer and a second protrusion facing the second wiring. The first protrusion is in the second recess. The second protrusion is in the first recess. The switching portion is configured to switch conductivity state according to voltage between the first wiring and the second wiring.

The disclosure is directed to spin-orbit torque MRAM structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.

A memory device includes; a memory cell array including a first memory cell region and a second memory cell region, a voltage generator configured to generate a code corresponding to a write voltage, and a write driver configured to store data in the first memory cell region in response to the code. The second memory cell region stores a value defining the write voltage, and the write voltage is determined in relation to a reference resistance distinguishing a parallel state and an anti-parallel state for the memory cells, and further in relation to an initial write voltage applied to a magnetic tunnel junction element of at least one of the memory cells.