The apparatus and the method for terahertz-based reading of data recorded in the Ruderman-Kittel-Kasuya-Yosida (RKKY)-based magnetic memory provided. The apparatus comprises: a Terahertz Magnon Laser configured to generate THz magnons; wherein the Terahertz Magnon Laser further comprises a Magnon Gain Medium (MGM) configured to support generation of non-equilibrium Terahertz magnons after the electric current is applied across the Terahertz Magnon Laser. The apparatus further comprises a magnetic reading bridge coupled to the Magnon Gain Medium of the Terahertz Magnon Laser; the magnetic reading bridge also coupled to a Ruderman-Kittel-Kasuya-Yosida (RKKY)-based magnetic memory cell; wherein magnetization of the magnetic reading bridge is induced by the overall magnetization of the RKKY)-based magnetic memory cell, and wherein the overall magnetization of the RKKY)-based magnetic memory cell is dependent on the information bit encoded into the magnetic memory cell, and wherein the encoded bit ‘1’ corresponds to the higher overall magnetization of the memory cell, and wherein the encoded bit ‘0’ corresponds to the lower overall magnetization of the memory cell. The apparatus further comprises a terahertz demodulator configured to demodulate the generated THz reading signal; wherein the higher detected THz frequency corresponds to reading bit ‘1’ encoded into the RKKY-based magnetic memory cell; and wherein the lower detected THz frequency corresponds to reading bit ‘0’ encoded into the RKKY-based magnetic memory cell.

A magnetoresistance effect element includes a wiring that extends in a first direction, a laminate that includes a first ferromagnetic layer connected to the wiring, a first conductive part and a second conductive part that sandwich the first ferromagnetic layer therebetween in a plan view in a lamination direction, and a resistor that has a geometrical center overlapping a geometrical center of the first conductive part or farther away from the laminate than the geometrical center of the first conductive part in the first direction when viewed in a plan view in the lamination direction.

Memory might include a controller configured to cause the memory to capacitively couple a first voltage level from a voltage node to a node of a sense circuit, selectively discharge the node of the sense circuit through a memory cell, measure a current demand of the voltage node while selectively discharging the node of the sense circuit through the memory cell, determine a second voltage level in response to the measured current demand, isolate the node of the sense circuit from the memory cell, capacitively couple the second voltage level from the voltage node to the node of the sense circuit, and determine a data state of the memory cell in response to a voltage level of the node of the sense circuit while capacitively coupling the second voltage level to the node of the sense circuit.

Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage at a first time duration to the memory array based on the read request. The control circuit is additionally configured to count a number of the plurality of memory cells that have switched to an active read state based on the first voltage and to derive a second time duration. The control circuit is further configured to apply a second voltage at the second duration to the memory array. The control circuit is also configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.

A neuromorphic device includes a plurality of cell tiles including a cell array including a plurality of memory cells storing a weight of a neural network, a row driver connected to the plurality of memory cells, and cell analog-digital converters connected to the plurality of memory cells and converting cell currents into a plurality of pieces of digital cell data, a reference tile including a plurality of reference cells, a reference row driver connected to the plurality of reference cells, and reference analog-digital converters connected to the plurality of reference cells and converting reference currents read via the plurality of reference column lines into a plurality of pieces of digital reference data, and a comparator circuit configured to compare the plurality of pieces of digital cell data with the plurality of pieces of digital reference data, respectively.

A read reference current generator includes a temperature coefficient (TC) controller configured to adjust a temperature coefficient in response to a first control signal and generate a read reference current having an adjusted temperature coefficient, a plurality of replica circuits configured to receive the read reference current and adjust an absolute value of the read reference current with different scale factors to generate a plurality of branch currents, and a plurality of switches configured to control connection of the TC controller and the plurality of replica circuits in response to a second control signal, wherein an equivalent resistance value of each of the plurality of replica circuits corresponds to a multiple of an equivalent resistance value of a data read path, and the data read path includes a selected memory cell and a clamping circuit clamping a voltage level of a selected bit line to a determined value.

The operation speed of a semiconductor device is improved. The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.

A magnetic memory device includes a conductive line extending in a first direction, a magnetic line extending in a second direction intersecting the first direction on the conductive line, the magnetic line intersecting the conductive line, and a magnetic pattern disposed between the conductive line and the magnetic line. The magnetic pattern has first sidewalls opposite to each other in the first direction, and second sidewalls opposite to each other in the second direction. The second sidewalls of the magnetic pattern are aligned with sidewalls of the conductive line, respectively.

A memory device has a plurality of bit cells, each of which includes an SRAM cell having a storage node selectively connectable to a first bit line in response to a control signal received on a first word line. Each bit cell further includes an MRAM cell selectively connectable to the storage node of the SRAM cell in response to a control signal received on a second word line.

This spin element includes: a current-carrying part that extends in a first direction; and an element part that is laminated on one surface of the current-carrying part, wherein the current-carrying part includes a first wiring and a second wiring in order from a side of the element part, and wherein both of the first wiring and the second wiring are metals and temperature dependence of resistivity of the first wiring is larger than temperature dependence of resistivity of the second wiring in at least a temperature range of −40° C. to 100° C.