A magnetoresistive random access memory (MRAM) device is provided. The MRAM device includes a main magnetic tunnel junction (MTJ) array comprising a plurality of memory cells configured to store memory data and a reference MTJ array comprising a plurality of reference cells having MTJ structures. The MRAM device further includes a controller operatively associated with the main MTJ array and the reference MTJ array. The controller is configured to receive a gross resistance of the reference MTJ array being related to a strength of an external magnetic field, determine whether the external magnetic field is fatal based on the received gross resistance of the reference MTJ array and a pre-determined threshold, and provide notification indicating that the memory data stored in the main MTJ array is untrustworthy if it is determined that the external magnetic field around the MRAM device is fatal.

A local data bus of a sense amplifier associated with one bit line is used to perform logical operations for a sensing operation performed by another sense amplifier associated with a different bit line. Each sense amplifier circuit includes a sensing node that is pre-charged, then discharged through a selected memory cell and a local data bus with a number of data latches connected. Target program data can be stored in the latches and combined in logical combinations with the sensed value of the memory cell to determine whether it has verified. By including a transfer circuit between the local data buses of a pair of sense amplifiers, the logical operations of a first sense amplifier can be performed using the local data bus of the paired sense amplifier, freeing the first sense amplifier's sense node to be concurrently pre-charged for a subsequent sensing operation, thereby improving performance.

A data-write device includes a write driver that causes a current to flow through a current path including an MTJ element or the other current path including the MTJ element in accordance with writing data to be written, thereby writing the write data into the MTJ element, a write completion detector which monitors the voltage at a first connection node or a second connection node in accordance with the write data after the writing of the write data into the MTJ element starts, detects the completion of writing of the write data based on the voltage at either node, and supplies a write completion signal indicating the completion of data write, and a write controller that terminates the writing of the write data into the MTJ element in response to the write completion signal supplied from the write completion detector.

According to one embodiment, a magnetic storage device includes a nonvolatile magnetic memory including a magnetoresistance effect element capable of storing data. A magnetic sensor is configured to measure the magnitude of an external magnetic field. A controller is configured to detect errors in the data at first time intervals when the measured magnitude of the external magnetic field is less than a threshold value and to detect errors in the data at second time intervals shorter than the first time interval when the measured magnitude of the external magnetic field is equal to or greater than the threshold value.

A variable resistance memory device includes: a memory cell including a first and second sub memory cell; and a first, second and third conductor. The first sub memory cell is above the first conductor, and includes a first variable resistance element and a first bidirectional switching element. The second sub memory cell is above the second conductor, and includes a second variable resistance element and a second bidirectional switching element. The second conductor is above the first sub memory cell. The third conductor is above the second sub memory cell. The variable resistance memory device is configured to receive first data and to write the first data to the memory cell when the first data does not match second data read from the memory cell.

A memory device includes a memory cell array, a read circuit, and a control logic. The memory cell array includes a memory cell having a resistance level that varies depending on data stored therein. The memory cell is connected to a first signal line and a second signal line. The read circuit is configured to read the data. The control logic is configured to precharge a sensing node, connected to the first signal line through a first switching device, and a first node, connected to the second signal line through a second switching device, to different voltage levels during a first period, and develop a voltage of the sensing node based on the resistance level of the memory cell during a second period.

A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). A storage layer has an anisotropic axis, in which the storage layer is configured to store a state in off axis positions and on axis positions. The off axis positions are not aligned with the anisotropic axis. A tunnel barrier is disposed on top of the storage layer. A ferromagnetic sense layer is disposed on top of the tunnel barrier.

A semiconductor storage device has a non-volatile memory, a memory controller to carry out write processing to the non-volatile memory using a write pulse, and a write pulse controller to select one of a first write mode for writing to the non-volatile memory and a second write mode for writing to the non-volatile memory with higher electric power consumption than the first write mode at higher speed than the first write mode and, when the first write mode is selected, set a pulse width of the write pulse such that the pulse width is shorter than one cycle of a clock signal used to control access to the non-volatile memory,

Some embodiments relate to a system that includes write circuitry, read circuitry, and comparison circuitry. The write circuitry is configured to attempt to write an expected multi-bit word to a memory location in a memory device. The read circuitry is configured to read an actual multi-bit word from the memory location. The comparison circuitry is configured to compare the actual multi-bit word read from the memory location with the expected multi-bit word which was previously written to the memory location to distinguish between a number of erroneous bits in the actual multi-bit word and a number of correct bits in the actual multi-bit word. The write circuitry is further configured to re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location.

According to one embodiment, a nonvolatile RAM includes an interface block, a memory cell array block, and a signal line connecting the interface block and the memory cell array block. The interface block comprises a command processing portion. The memory cell array block comprises a memory cell array, an access circuit accessing the memory cell array, a read circuit reading read data from the memory cell array, a write circuit writing write data to the memory cell array, and a write control circuit controlling a read operation using the read circuit and a first write operation using the write circuit following the read operation without changing a selected word line in the memory cell array.