A data processing system may include a plurality of memory modules, a controller, a power supply and a plurality of switches. Each of the memory modules may include a plurality of pages. The controller may control operations of the memory modules. The power supply may provide the memory modules with a power. The switches may be arranged corresponding to each of the memory modules. The switches may be selectively driven in response to a switch drive signal from the controller.

A memory includes at least one resistive memory cell and a write device. The memory cell includes a memory element having at least a highly resistive state and a lowly resistive state, and a selector arranged in series with the memory element, the selector being electrically conductive when a voltage greater than a given threshold voltage is applied to the selector. The write device includes at least one write capacitor and one charging device, and is configured to charge the write capacitor and then to connect it to the memory cell to program that cell.

A device with a neural network includes: a synaptic memory cell comprising a resistive memory element, which is disposed along an output line and which has either one of a first resistance value and a second resistance value, and configured to generate a column signal based on the resistive memory element and an input signal in response to the input signal being received through an input line; a reference memory cell comprising a reference memory element, which is disposed along a reference line and which has the second resistance value different from the first resistance value, and configured to generate a reference signal based on the reference memory element and the input signal; and an output circuit configured to generate an output signal for the output line from the column signal and the reference signal.

An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.

According to one embodiment, a memory system includes a shift register memory and a controller. The shift register memory includes data storing shift strings. The controller changes a shift pulse, which is to be applied to the data storing shift strings from which first data is read by applying a first shift pulse, to a second shift pulse to write second data to the data storing shift strings and to read the second data from the data storing shift strings. The controller creates likelihood information of data read from the data storing shift strings in accordance with a read result of the second data. The controller performs soft decision decoding for the first data using the likelihood information.

A first memory cell is coupled to first and third interconnects. A second memory cell is coupled to second and fourth interconnects. A first sense amplifier has a first terminal coupled to the first interconnect and a node of a first potential and a second terminal located close to a node of a second potential and coupled to the third interconnect and has a potential difference between the first and second terminals. A second sense amplifier has a third terminal coupled to the fourth interconnect and a node of a third potential and a fourth terminal located close to a node of a fourth potential and coupled to the second interconnect and has a potential difference between the third and fourth terminals.

An apparatus includes a perpendicular magnetic tunnel junction (MTJ) including a free layer. The apparatus includes a spin orbit torque metal layer coupled to the perpendicular MTJ and configured to change a magnetization state of the free layer responsive to flow of a current along the spin orbit torque metal layer. The apparatus includes a random number generator configured to generate a random number at least partially based on a state of the perpendicular MTJ.

In a memory, a first node holds first data from a first cell. A second node holds second data from a second cell near the first cell. A differential circuit includes a first current path passing a first current corresponding to a voltage of the first node and a second current path passing a second current corresponding to a voltage of the second node, and outputs an output signal corresponding to a voltage difference between the first and the second nodes from an output part. A first register latches the output signal and output the signal as a hold signal. A first offset part is connected to the first current path and offsets the first current when the hold signal has a first logic level. A second offset part is connected to the second current path and offsets the second current when the hold signal has a second logic level.

What is specified is a method for transforming a first binary signal read from a memory, wherein the first binary signal is transformed into a second binary signal provided that the first binary signal is a code word or a predefined code word of a k-out-of-n code, wherein the first binary signal is transformed into a predefined signal provided that the first binary signal is not a code word or is not a predefined code word of the k-out-of-n code, wherein the predefined signal is different than the second binary signal. A corresponding device is furthermore specified.

According to one embodiment, a memory device includes first and second lines, a memory cell connected between the first and second lines, and including a resistance change memory element and a switching element, a current supply circuit supplying write current to the memory cell when data is written to the resistance change memory element, a detection circuit detecting an on state of the switching element after supply operation of the write current is enabled, and a control circuit controlling a time required until supplying the write current from the current supply circuit is stopped, wherein a starting point of the controlling the time is a time point at which the on state of the switching element is detected.