A physically unclonable function magnetic memory device includes a plurality of magnetic resistance cells disposed on a substrate and each including a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer or a non-magnetic conductive layer interposed between the pinned magnetic layer and the free magnetic layer. In an operating method of the physically unclonable magnetic memory device, an external magnetic field, decaying with time, is applied to the plurality of magnetic resistance cells to randomize a magnetization direction of the free magnetic layer of each of the plurality of magnetic resistance cells.

According to one embodiment, a magnetic storage device includes a nonvolatile magnetic memory including a magnetoresistance effect element capable of storing data. A magnetic sensor is configured to measure the magnitude of an external magnetic field. A controller is configured to detect errors in the data at first time intervals when the measured magnitude of the external magnetic field is less than a threshold value and to detect errors in the data at second time intervals shorter than the first time interval when the measured magnitude of the external magnetic field is equal to or greater than the threshold value.

In a non-limiting embodiment, a magnetic memory device includes a memory component having a plurality of magnetic storage elements for storing memory data, and one or more sensor components configured to detect a magnetic field external to the memory component. The sensor component outputs a signal to one or more components of the magnetic memory device based on the detected magnetic field. The memory component is configured to be terminated when the signal is above a predetermined threshold value. In some embodiments, a magnetic field is generated in a direction opposite to the direction of the detected external magnetic field when the signal is above the predetermined threshold value.

A memory system in an integrated circuit and a method of operation. The system includes multiple magnetic tunnel junction (MTJ) structures, each MTJ structure storing a logic value according to a resistive state. A selection switch device associated with a respective MTJ structure is activated to select one of the multiple MTJ structures at a time. An output circuit is configured to sense the resistive state of a selected MTJ structure, the output circuit having a selectable input reference resistance value according to a selected first reference resistance or a second reference resistance value, and outputting a first logic value of the selected MTJ structure responsive to a resistive state of the MTJ structure and a selected first resistance reference value, or alternately outputting a second logic value of the selected MTJ structure responsive to the resistive state of the MTJ structure and a selected second resistance reference value.

A physically unclonable function (PUF) generator includes a first sense amplifier that has a first input terminal configured to receive a signal from a first memory cell of a plurality of memory cells, and a second input terminal configured to receive a signal from a second memory cell of the plurality of memory cells. The first sense amplifier is configured to compare accessing speeds of the first and second memory cells of the plurality of memory cells. Based on the comparison of the accessing speeds, the sense amplifier provides a first output signal for generating a PUF signature. A controller is configured to output an enable signal to the first sense amplifier, which has a first input terminal configured to receive a signal from a bit line of the first memory cell and a second input terminal configured to receive a signal from a bit line of the second memory cell.

A non-volatile memory device includes: a memory group of a plurality of variable resistance memory cells in which digital data is recorded according to a magnitude of a resistance value, the memory group including at least one data cell and at least one dummy cell which are associated with each other; and a read circuit which performs, in parallel, a read operation on each of the plurality of memory cells included in the memory group. Dummy data, for reducing a correlation between a side-channel leakage generated when the read operation is performed by the read circuit and information data recorded in the at least one data cell, is recorded in the at least one dummy cell.

A method for compensating for external magnetic fields in memory devices that includes positioning at least one external magnetic field sensing element adjacent to at least one array of memory cells, wherein a write driver is in electrical communication with at least one external magnetic field sensing element and at least one array of memory cells. The at least one external magnetic field sensing element is monitored for signals indicative of the present of an external magnetic field. The write current to the at least one array of memory cells can be adjusted by trimming the write driver to operate the memory device while compensating for the external magnetic field.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

The present disclosure is drawn to, among other things, an antifuse circuit. The antifuse circuit includes a plurality of antifuse bitcells and a reference resistor. Each antifuse bitcell includes two or more memory bits and a reference resistor. The two or more memory bits are configured to be in a programmed state and at least one unprogrammed state.

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.