A magnetic recording array according to the present embodiment includes a plurality of spin elements, a first reference cell, and a second reference cell, wherein the plurality of spin elements, the first reference cell, and the second reference cell each have a wiring and a stacked body including a first ferromagnetic layer stacked on the wiring, wherein the electrical resistance of the wiring of the first reference cell is higher than the electrical resistance of the wiring of each spin element, and wherein the electrical resistance of the wiring of the second reference cell is lower than the electrical resistance of the wiring of each spin element.

A highly reliable STT-MRAM structure and an implementation method thereof are provided. The STT-MRAM structure includes: a memory block array, including a plurality of memory blocks; on-chip in-situ temperature sensors, for detecting an instantaneous temperature of each memory block; and a controller, which outputs a reading or writing operation signal based on the instantaneous temperature of each memory block detected by the on-chip in-situ temperature sensors, so as to modulate respective voltages and/or frequencies of reading and writing operations of each memory block. When the instantaneous temperature is too high, the voltages and/or frequencies of the reading and writing operations would be decreased, to the contrary when the instantaneous temperature is too low, the voltages and/or frequencies of the reading and writing operations would be increased, which expands a reliable working temperature range and lengthens a lifetime of the STT-MRAM structure.

A nonvolatile memory device includes; a memory cell array including memory cells connected with bit lines and feedback cells connected with feedback bit lines, a row decoder connected with the memory cells and the feedback cells through word lines, a column decoder connected with the memory cells through the bit lines and connected with the feedback cells through the feedback bit lines, and a charge pump that generates a pump voltage provided to a selected word line among the word lines, wherein the charge pump is controlled in response to feedback currents flowing through the feedback bit lines.

Various implementations described herein are directed to device having a memory block and a sense amplifier coupled to the memory block. The device may include a bias generator that applies a bias signal to the sense amplifier for regulating read current to the sense amplifier for faster activation of the memory block.

A power regulation system including a reference generator, a temperature compensation circuit coupled to the reference generator, and a low-dropout (LDO) regulator circuit coupled to the temperature compensation circuit, wherein the temperature compensation circuit provides a reference voltage to the LDO regulator circuit at least based on a ratio of a first current and a second current.

A data processing system may include a plurality of memory modules, a controller, a power supply and a plurality of switches. Each of the memory modules may include a plurality of pages. The controller may control operations of the memory modules. The power supply may provide the memory modules with a power. The switches may be arranged corresponding to each of the memory modules. The switches may be selectively driven in response to a switch drive signal from the controller.

The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin.

A memory cell is coupled between first and interconnects and includes a variable resistance element and a switching element. The variable resistance element includes first and second ferromagnetic layers and an insulating layer between the first and second ferromagnetic layers. A first circuit is configured to apply a first voltage to the first interconnect. A second circuit is configured to apply a second voltage to the second interconnect. A third circuit is configured to apply a third voltage to the second interconnect. A fourth circuit is configured to apply a fourth voltage to the first interconnect. A sense amplifier circuit is coupled to the first and second interconnects.

A memory circuit includes a bias voltage generator including a first buffer configured to generate a first bias voltage based on a reference voltage and a plurality of second buffers configured to generate a plurality of second bias voltages based on the first bias voltage. The memory circuit includes a plurality of voltage clamp devices coupled to the plurality of second buffers, and each voltage clamp device is configured to apply a drive voltage to a corresponding resistance-based memory device of a plurality of resistance-based memory devices based on the corresponding second bias voltage of the plurality of second bias voltages.

Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.