Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic de-multiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices.

In an embodiment, a voltage regulation circuit includes a regulation circuit with a voltage regulator that provides an output voltage and a control circuit, coupled to the voltage regulator. The control circuit pulls up the output voltage to a reference voltage responsive to the control circuit detecting that a first voltage level of the output voltage is lower than a predefined voltage level. The control circuit decouples the output voltage from the reference voltage responsive to the control circuit detecting that the first voltage level of the output voltage is higher than the predefined voltage level.

An integrated circuit device is provided. The integrated circuit device includes: a functional device including a selection device; and a bias generator circuit coupled to the selection device and configured to detect a leakage current of the functional device and generate a bias voltage based on the detected leakage current. The bias voltage is provided to the selection device to control the selection device.

A write voltage generator is connected with a magnetoresistive random access memory. The write voltage generator provides a write voltage during a write operation. A storage state of a selected memory cell in a write path of the magnetoresistive random access memory is changed in response to the write voltage. The write voltage generator includes a temperature compensation circuit and a process corner compensation circuit. The temperature compensation circuit generates a transition voltage according to an ambient temperature. The transition voltage decreases with the increasing ambient temperature. The process corner compensation circuit receives the transition voltage and generates the write voltage.

A memory device includes a well, a poly layer, a dielectric layer, an alignment layer and an active area. The poly layer is formed above the well. The dielectric layer is formed above the poly layer. The alignment layer is formed on the dielectric layer, used to receive an alignment layer voltage and substantially aligned with the dielectric layer in a projection direction. The active area is formed on the well. The dielectric layer is thicker than the alignment layer. A first overlap area of the poly layer and the active area is smaller than a second overlap area of the poly layer and the dielectric layer excluding the first overlap area.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

A method for receiving autonomous vehicle (AV) map data associated with an AV map of a geographic location and coverage map data associated with a coverage map of the geographic location. The AV map data is associated with an AV lane of a roadway in the geographic location, and the coverage map data is associated with a coverage lane of the roadway in the geographic location. The method includes generating a hybrid map of the geographic location based on the AV map data and the coverage map data and providing hybrid map data associated with the hybrid map for routing of an AV. The hybrid map includes the AV lane linked with the coverage lane of the roadway.

According to one embodiment, a memory device includes: a first and a second interconnects; a memory cell including a variable resistive element, the memory cell between the first and second interconnects; and a write circuit including a current source circuit and a voltage source circuit, the write circuit writing data to the memory cell by using a write pulse. The write circuit supplies the write pulse to the memory cell by using the current source circuit in a first period from a first time of a start of supply of the write pulse to a second time, and supplies the write pulse to the memory cell by using the voltage source circuit in a second period from a third time to a fourth time of an end of the supply of the write pulse.

A random bit cell includes a selection transistor, a first P-type transistor, and a second P-type transistor. The selection transistor has a first terminal coupled to a source line, a second terminal coupled to a common node, and a control terminal coupled to a word line. The first P-type transistor has a first terminal coupled to the common node, a second terminal coupled to a first bit line, and a floating gate. The second P-type transistor has a first terminal coupled to the common node, a second terminal coupled to a second bit line, and a floating gate. During an enroll operation, one of the first P-type transistor and the second P-type transistor is programmed by channel hot electron injection.

In an embodiment, a voltage regulation circuit includes a regulation circuit with a voltage regulator that provides an output voltage and a control circuit, coupled to the voltage regulator. The control circuit pulls up the output voltage to a reference voltage responsive to the control circuit detecting that a first voltage level of the output voltage is lower than a predefined voltage level. The control circuit decouples the output voltage from the reference voltage responsive to the control circuit detecting that the first voltage level of the output voltage is higher than the predefined voltage level.