A magnetic tunnel junction may include a platinum-containing layer including at least one of Ir, Hf or Ru in contact with a free layer, or a combination of a platinum layer and a Hf or Ir layer formed on opposite sides of a free layer.

A method for receiving autonomous vehicle (AV) map data associated with an AV map of a geographic location and coverage map data associated with a coverage map of the geographic location. The AV map data is associated with an AV lane of a roadway in the geographic location, and the coverage map data is associated with a coverage lane of the roadway in the geographic location. The method includes generating a hybrid map of the geographic location based on the AV map data and the coverage map data and providing hybrid map data associated with the hybrid map for routing of an AV. The hybrid map includes the AV lane linked with the coverage lane of the roadway.

A power switch circuit and non-volatile memory device including the same are provided. The power switch circuit includes a multi-voltage providing circuit configured to receive a first voltage and a second voltage greater than the first voltage, output a third voltage corresponding to the first voltage to a first output terminal, and output a fourth voltage corresponding to the second voltage to a second output terminal. The power switch circuit also includes a leakage current prevention circuit configured to cut off a leakage current flowing through the multi-voltage providing circuit. The multi-voltage providing circuit includes a first inverter which is driven using the second voltage. The leakage current prevention circuit is configured to cut off the leakage current flowing through the first inverter in response to both the first voltage and the second voltage being provided to the multi-voltage providing circuit.

A bias voltage generator includes a first current path, a first voltage clamp device, and a first buffer. The bias voltage generator receives a reference voltage and generates a first bias voltage based on a voltage difference between the reference voltage and a first drive voltage, the first voltage clamp device generates the first drive voltage based on the first bias voltage by applying the first drive voltage to the first current path, and the first buffer receives the first bias voltage and generates a second bias voltage based on the first bias voltage. A second current path includes a resistance-based memory device, and a second voltage clamp device generates a second drive voltage based on the second bias voltage and applies the second drive voltage to the second current path.

For a buck-boost DC-DC converter with n-type high-side field effect transistor (HSFET), a supply is derived from input and output rails, and this supply maintains a constant differential voltage independent of input supply voltage. The derived supply is used as the high supply (HS) of an HSFET Driver. As such, the HSFET resistance becomes independent of supply variation. A wide range ultra-low IQ (Quiescent current), edge triggered level-shifter provides support to a bootstrapped power stage of the inverting buck-boost DC-DC converter. When p-type HSFET is used, a supply is derived from the input and output supply rails, and this derived supply maintains a constant differential voltage independent to the input supply voltage. The derived supply is used as the low supply (LS) or ‘ground’ of the HSFET Driver. As such, the p-type HSFET resistance becomes independent of supply variation.

This spin current magnetization rotational type magnetoresistive element includes a magnetoresistive effect element having a first ferromagnetic metal layer having a fixed magnetization orientation, a second ferromagnetic metal layer having a variable magnetization orientation, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer, and spin-orbit torque wiring which extends in a direction that intersects the stacking direction of the magnetoresistive effect element, and is connected to the second ferromagnetic metal layer, wherein the electric current that flows through the magnetoresistive effect element and the electric current that flows through the spin-orbit torque wiring merge or are distributed in the portion where the magnetoresistive effect element and the spin-orbit torque wiring are connected.

Metal-oxide semiconductor (MOS) transistor offset-cancelling (OC), zero-sensing (ZS) dead zone, current-latched sense amplifiers (SAs) (CLSAs) (OCZS-SAs) for sensing differential voltages are provided. An OCZS-SA is configured to amplify received differential data and reference input voltages with a smaller sense amplifier offset voltage to provide larger sense margin between different storage states of memory bitcell(s). The OCZS-SA is configured to cancel out offset voltages of input and complement input transistors, and keep the input and complement input transistors in their activated state during sensing phases so that sensing is not performed in their “dead zones” when their gate-to-source voltage (Vgs) is below their respective threshold voltages. In other aspects, sense amplifier capacitors are configured to directly store the data and reference input voltages at gates of the input and complement input transistors during voltage capture phases to avoid additional layout area that would otherwise be consumed with additional sensing capacitor circuits.

Dynamically controlling voltage for access (i.e., read and/or write) operations to magneto-resistive random access memory (MRAM) bit cells to account for process variations is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations in MTJs that affect MTJ resistance, which can change write current at a given fixed supply voltage applied to an MRAM bit cell. The MRAM bit cell PVMC may also be configured to measure process variations in logic circuits representing process variations in access transistors employed in MRAM bit cells. These measured process variations in MTJs and/or logic circuits are used to dynamically determine a supply voltage for access operations to MRAM.

A method of controlling a memory device can include: determining, by the memory device, a time duration in which the memory device is in a standby mode; automatically switching the memory device from the standby mode to a power down mode in response to the time duration exceeding a predetermined duration; exiting from the power down mode in response to signaling from a host device via an interface; and toggling a data strobe when data is ready to be output from the memory device in response to a read command from the host device.

Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.