Methods, systems, and devices for deck-level signal development cascodes are described. A memory device may include transistors that support both a signal development and decoding functionality. In a first operating condition (e.g., an open-circuit condition), a transistor may be operable to isolate first and second portions of an access line based on a first voltage applied to a gate of the transistor. In a second operating condition (e.g., a signal development condition), the transistor may be operable to couple the first and second portions of the access line and generate an access signal based on a second voltage applied to the gate of the transistor. In a third operating condition (e.g., a closed-circuit condition), the transistor may be operable to couple the first and second portions of the access line based on applying a third voltage greater than the second voltage to the gate of the transistor.

Disclosed is a content addressable memory device including a memory cell array including a plurality of memory cells, each of which has a ferroelectric tunnel field effect transistor (FeTFET), and a match amplifier connected to the plurality of memory cells through a plurality of match lines. The FeTFET includes a first doped region including a first conductivity type, a second doped region including a second conductivity type different from the first conductivity type, a channel region formed between the first doped region and the second doped region, and a gate formed on the channel region and including a ferroelectric layer.

Methods, systems, and devices for power gating in a memory device are described for using one or more memory cells as drivers for load circuits of a memory device. A group of memory cells of the memory device may represent memory cells that include a switching component and that omit a memory storage element. These memory cells may be coupled with respective plate lines that may be coupled with a voltage source having a first supply voltage. Each memory cell of the group may also be coupled with a respective digit line that may be coupled with the load circuits. Respective switching components of the group of memory cells may therefore act as drivers to apply the first supply voltage to one or more load circuits by coupling a digit line with a plate line having the first supply voltage.

Methods, systems, and devices for access line disturbance mitigation are described to, for example, reduce voltage disturbances on deselected digit lines during a read or write operation. Memory cells of a memory device may be couplable with a write circuit including a level shifter circuit, such that changes in voltage on a selected digit line may be controlled via a level shifter circuit of a write circuit associated with a selected memory cell. The write circuit may write a logic state to the memory cell after completing a read operation. One or more write voltages may be applied to or removed from the memory cell via the level shifter circuit, which may control a slew rate of one or more voltage changes on the selected digit line. The slew rate(s) may be controlled via a current driver circuit coupled with a pull-up circuit or a pull-down circuit of the level shifter circuit.

A memory cell arrangement is provided that may include: a plurality of first control lines; a plurality of second control lines; a plurality of third control lines; each of a plurality of memory cell sets includes memory cells and is assigned to a corresponding one of the plurality of first control lines and includes at least a first memory cell subset addressable via the corresponding first control line, a corresponding one of the plurality of second control lines, and the plurality of third control lines, and at least a second memory cell subset addressable via the corresponding first control line, the plurality of second control lines, and a corresponding one of the plurality of third control lines. The corresponding one of the plurality of third control lines addresses the second memory cell subset of each memory cell set of the plurality of memory cell sets.

Methods, systems, and devices for deck-level shunting in a memory device are described. A memory device may include memory arrays arranged in a stack of decks over a substrate, and a combination of deck selection circuitry and shunting circuitry may be distributed among the decks to leverage common substrate-based circuitry, such as logic or addressing circuitry. For example, each memory array of a stack may include a set of digit lines and deck selection circuitry, such as deck selection transistors or other switching circuitry, operable to couple the set of digit lines with a column decoder that may be shared among multiple decks. Each memory array of a stack also may include shunting circuitry, such as shunting transistors or other switching circuitry operable to couple the set of digit lines with a plate node, thereby equalizing a voltage across the memory cells of the respective memory array.

In some embodiments, a memory device implements a tile-based architecture including an arrangement of independently and concurrently operable arrays or tiles of memory transistors where each tile includes memory transistors that are arranged in a three-dimensional array and a localized modular control circuit operating the memory transistors in the tile. The tile-based architecture of the memory device enables concurrent memory access to multiple tiles, which enables independent and concurrent memory operations to be carried out across multiple tiles. The tile-based concurrent access to the memory device has the benefits of increasing the memory bandwidth and lowering the tail latency of the memory device by ensuring high availability of storage transistors. In other embodiments, a memory module includes multiple semiconductor memory dies coupled to a memory controller where the semiconductor memory dies are partitioned into independently accessible memory channels with each memory channel being formed across the multiple semiconductor memory dies.

Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.

Methods, systems, and devices for operating a memory device are described. One method includes caching data of a memory cell at a sense amplifier of a row buffer upon performing a first read of the memory cell; determining to perform at least a second read of the memory cell after performing the first read of the memory cell; and reading the data of the memory cell from the sense amplifier for at least the second read of the memory cell.

Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.