A memory device includes metal interconnect structures embedded within dielectric material layers that overlie a top surface of a substrate, a thin film transistor embedded in a first dielectric material layer selected from the dielectric material layers, and is vertically spaced from the top surface of the substrate, and a ferroelectric memory cell embedded within the dielectric material layers. A first node of the ferroelectric memory cell is electrically connected to a node of the thin film transistor through a subset of the metal interconnect structures that is located above, and vertically spaced from, the top surface of the substrate.

The disclosed technology is generally directed to semiconductor integrated circuit devices and more particularly to a three-transistor random access memory (3T RAM) device, and a method of fabricating and operating the same. In one aspect, a 3T RAM cell includes a ferroelectric-based field effect transistor (FeFET) having a first gate connected as a storage node and a second transistor connected between the FeFET and a read bit line having a second gate connected to a read word line. The 3T RAM cell also includes a third transistor connected between the storage node and a write bit line having a third gate connected to a write word line.

Methods, systems, and devices for protecting stored data in a memory device are described. In one example, a memory device may include a set of memory cells coupled with a digit line and a plate line. A method of operating the memory device may include performing an access operation on a selected memory cell of the set of memory cells, and performing an equalization operation on a non-selected memory cell of the plurality of memory cells based on performing the access operation. The equalization operation may include applying an equal voltage to opposite terminals of the non-selected memory cell via the digit line and the plate line, which may allow built-up charge, such as leakage charge resulting from the access operation, to dissipate. Such an equalization operation may reduce a likelihood of memory loss in non-selected memory cells after access operations.

A semiconductor structure includes a substrate, an interconnection structure disposed over the substrate and a first memory cell. The first memory cell is disposed over the substrate and embedded in dielectric layers of the interconnection structure. The first memory cell includes a first transistor and a first data storage structure. The first transistor is disposed on a first base dielectric layer and embedded in a first dielectric layer. The first data storage structure is embedded in a second dielectric layer and electrically connected to the first transistor. The first data storage structure includes a first electrode, a second electrode and a storage layer sandwiched between the first electrode and the second electrode.

A memory device includes a plurality of memory cells. Each memory cell includes a multi-gate FeFET that has a first source/drain terminal, a second source/drain terminal, and a gate with a plurality of ferroelectric layers configured such that each of the ferroelectric layers has a respective unique switching E-field.

Methods, systems, and devices for a read algorithm for a memory device are described. When performing a read operation, the memory device may access a memory cell to retrieve a value stored by the memory cell. The memory device may compare a set of reference voltages with a signal output by the memory cell based on accessing the memory cell. Thus, the memory device may determine a set of candidate values stored by the memory cell, where each candidate value is associated with one of the reference voltages. The memory device may determine and output the value stored by the memory cell based on determining the set of candidate values. In some cases, the memory device may determine the value stored by the memory cell based on performing an error control operation on each of the set of candidate values to detect a quantity of errors within each candidate value.

Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.

One example provides a memory cell including a node, and a layer stack including a first electrode, a second electrode connected to the node, and a polarizable material layer disposed between the first and second electrodes and having at least two polarization states. A first transistor includes a source, a drain, and a gate terminal, with the gate terminal connected to the node. A selector element includes at least a first terminal and a second terminal, with the second terminal connected to the node.

A semiconductor storage device includes a stacked body and a columnar body. The stacked body includes a plurality of conductive layers spaced apart from each other in a stacking direction. The columnar body penetrates the stacked body in the stacking direction. The columnar body includes a columnar ferroelectric film, a semiconductor film disposed between the ferroelectric film and the conductive layers, and an insulating film disposed between the semiconductor film and the conductive layers.

Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. In some examples, the duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.