A programming method for a three-dimensional ferroelectric memory device is disclosed. The programming method includes applying a first voltage on a selected word line of a target memory cell. The target memory cell has a first logic state and a second logic state corresponding to a first threshold voltage and a second threshold voltage, respectively. The first and second threshold voltages are determined by two opposite electric polarization directions of a ferroelectric film in the target memory cell. The programming method also includes applying a second voltage on a selected bit line, where a voltage difference between the first and second voltages has a magnitude larger than a coercive voltage of the ferroelectric film such that the target memory cell is switched from the first logic state to the second logic state.

An oxide semiconductor-based FRAM is provided in the present invention, including a substrate, a word line on the substrate, a gate insulating layer on the word line, an oxide semiconductor layer on the gate insulating layer, a source and a drain respectively on the oxide semiconductor layer and spaced apart at a distance, wherein the source and the drain further connect respectively to a plate line and a bit line, a ferroelectric dielectric layer on the source, the drain and the oxide semiconductor layer, and a write electrode on the ferroelectric dielectric layer, wherein the write electrode, the ferroelectric dielectric layer, the oxide semiconductor layer, the gate insulating layer and the word line overlap each other in a direction vertical to the substrate.

Methods, systems, and devices for access line management for an array of memory cells are described. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended cross-coupling between various components of the memory device may be significant. To mitigate the impact of unintended cross-coupling between various components, the memory device may float unselected word lines during one or more portions of an access operation. Accordingly, a voltage of each unselected word line may relate to the voltage of the plate as changes in plate voltage may occur.

Methods, systems, and devices for voltage drop mitigation techniques for memory devices are described. A memory device may include an array of memory cells, a conductive line, a pull-up circuit, and an output circuit. The conductive line may be configured to convey a first voltage for performing an operation with the array of memory cells. The pull-up circuit may be configured to couple the conductive line with a voltage source during at least a portion of a duration in which the operation is performed based on a first signal that enables applying a current to the array of memory cells as part of the operation. The output circuit may be configured to output a second signal to deactivate the pull-up circuit before the operation is complete. Outputting the second signal may be based on the first signal and a difference between the first voltage and a reference voltage.

A method includes providing a substrate including a channel region, the substrate comprising a two-stage structure having a first surface, a second surface higher than the first surface and a third surface connected between the first surface and the second surface; covering the substrate from a top thereof with an oxide layer; forming a ferroelectric material strip on a topmost surface of the oxide layer; and forming a gate strip covering the ferroelectric material strip and the oxide layer from a top of the gate strip.

Memory cells are described that include two reference voltages that may store and sense three distinct memory states by compensating for undesired intrinsic charges affecting a memory cell. Although embodiments described herein refer to three memory states, it should be appreciated that in other embodiments, the memory cell may store or sense more than three charge distributions using the described methods and techniques. In a first memory state, a programming voltage or a sensed voltage may be higher than a first reference voltage and a second reference voltage. In a second memory state, the applied voltage or the sensed voltage may be between the first and the second reference voltages. In a third memory state, the applied voltage or the sensed voltage may be lower than the first and the second reference voltages. As such, the memory cell may store and retrieve three memory states.

Methods, systems, and devices for biasing techniques, such as open page biasing techniques, are described. A memory cell may be accessed during an access phase of an access operation, for example, an open page access operation. An activate pulse may be applied to the memory cell during the access phase. The memory cell may be biased to a non-zero voltage after applying the activate pulse and before a pre-charge phase. The pre-charge phase of the access phase may be initiated after biasing the memory cell to the non-zero voltage.

A memory cell arrangement is provided that may include: at least one memory cell and a read-out circuit. The memory cell includes a first terminal, a second terminal, a third terminal, and a field-effect transistor structure being connected to the first terminal, the second terminal, and the third terminal. The read-out circuit is configured to carry out a read-out operation to read out a memory state of the memory cell, the read-out operation including: providing a first voltage at the first terminal, a second voltage at the second terminal, and a third voltage at the third terminal such that the field-effect transistor structure is in a high-resistivity state and such that a leakage current through the first terminal and/or through the second terminal is generated, and sensing the leakage current to determine the memory state of the memory element.

Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a selection component to discharge. Access operations may also be timed to allow residual charge of middle electrodes associated with other cells to be discharged. In conjunction with an access operation for a target cell, a residual charge of a middle electrode of another cell may be discharged, and the target cell may then be accessed. A capacitor in electronic communication with a cell may be charged and a logic state of the cell determined based on the charge of the capacitor. The timing for charging the capacitor may be related to the time for discharging a middle electrode of the cell or another cell.

Memories are provided. A memory includes a plurality of ferroelectric random access memory (FRAM) cells arranged in a first memory array, and a plurality of static random access memory (SRAM) cells arranged in a second memory array. The first memory array and the second memory array share the same bus. Each of the FRAM cells includes a ferroelectric field-effect transistor (FeFET). A gate structure of the FeFET includes a gate electrode over a channel of the FeFET, and a ferroelectric layer over the gate electrode.