Methods, systems, and devices for sensing techniques for differential memory cells are described. A method may include selecting a pair of memory cells that comprise a first memory cell coupled with a first digit line and a second memory cell coupled with a second digit line for a read operation, the pair of memory cells storing one bit of information. The method may further include applying a first voltage to a plate line coupled with the first memory cell and the second memory cell and applying a second voltage to a select line to couple the first digit line and the second digit line with a sense amplifier. The amplifier may sense a logic state of the pair of memory cells based on a difference between a third voltage of the first digit line and a fourth voltage of the second digit line.

Methods, systems, and devices for cell data bulk reset are described. In some examples, a logic state (e.g., a first logic state) may be written to one or more memory cells based on an associated memory device transitioning power states. To write the first logic state to the memory cells, a first subset of digit lines may be driven to a first voltage and a plate may be driven to a second voltage. While the digit lines and plate are driven to the respective voltages, one or more word lines may be driven to the second voltage. In some instances, the word lines may be driven to the second voltage based on charge sharing occurring between adjacent word lines.

Methods, systems, and apparatuses for self-referencing sensing schemes are described. A cell having two transistors, or other switching components, and one capacitor, such as a ferroelectric capacitor, may be sensed using a reference value that is specific to the cell. The cell may be read and sampled via one access line, and the cell may be used to generate a reference voltage and sampled via another access line. For instance, a first access line of a cell may be connected to one read voltage while a second access line of the cell is isolated from a voltage source; then the second access line may be connected to another read voltage while the first access line is isolate from a voltage source. The resulting voltages on the respective access lines may be compared to each other and a logic value of the cell determined from the comparison.

Systems and methods for confirming the presence of a person or asset for a given purpose, and recording this information in a distributed ledger. The distributed ledger records and confirms presence indicia in connection with a transaction said facilitates remote and/or automated signatures. The systems and methods detect the presence of one or more humans and/or computing devices at a specific location at the time of a transaction, and contemporaneously recording information concerning the transaction in a distributed ledger. Presence can be determined using network presence sensing (NPS), other types of sensors, or the combination of NPS with other sensors.

The present disclosure provides a memory device, which includes a plurality of electrically bipolar variable memory devices and a storage transistor. The electrically bipolar variable memory devices are electrically connected to a plurality of word lines respectively, the storage transistor is electrically connected to the electrically bipolar variable memory devices, where one end of each of the electrically bipolar variable memory devices is electrically connected to a corresponding one of the word lines, and another end of each of the electrically bipolar variable memory devices is electrically connected to the gate of the storage transistor.

Methods, systems, and devices for a read algorithm for a memory device are described. When performing a read operation, the memory device may access a memory cell to retrieve a value stored by the memory cell. The memory device may compare a set of reference voltages with a signal output by the memory cell based on accessing the memory cell. Thus, the memory device may determine a set of candidate values stored by the memory cell, where each candidate value is associated with one of the reference voltages. The memory device may determine and output the value stored by the memory cell based on determining the set of candidate values. In some cases, the memory device may determine the value stored by the memory cell based on performing an error control operation on each of the set of candidate values to detect a quantity of errors within each candidate value.

A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.

Some embodiments include an integrated assembly having a semiconductor structure extending from a first wiring to a second wiring. A ferroelectric transistor includes a first transistor gate adjacent a first region of the semiconductor structure. A first non-ferroelectric transistor includes a second transistor gate adjacent a second region of the semiconductor structure. The second region of the semiconductor structure is between the first region of the semiconductor structure and the first wiring. A second non-ferroelectric transistor includes a third transistor gate adjacent a third region of the semiconductor structure. The third region of the semiconductor structure is between the first region of the semiconductor structure and the second wiring.

Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.

Various aspects relate to a multiply and accumulate circuit, the multiply and accumulate circuit including: a plurality of multiply operation cells configured in a matrix arrangement. A respective multiply operation cell of the multiply operation cells includes: a field-effect transistor and a programmable switch in a series connection, wherein the field-effect transistor and the programmable switch are configured to control a current flow through the respective multiply operation cell to realize a multiplication operation. The multiply operation cells of a set of the plurality of multiply operation cells share a corresponding control line to realize an accumulation operation in addition to the multiply operations carried out by the set of multiply operation cells.